System Address Space
A–39
Scatter-Gather Addressing
Each scatter-gather map page table entry (PTE) is a quadword and has a valid bit in
bit position 0, as shown in Figure 1–19. Address bit 13 is at bit position 1 of the map
entry. Because the 21174 implements valid memory addresses up to 16GB, then bits
<63:22> of the scatter-gather map entry must be programmed to 0. Bits <21:1> of
the scatter-gather map entry are used to generate the physical page address. The
physical page address is appended to ad<12:5> of the incoming PCI address to gen-
erate the memory address.
System implementations may support less than 16GB of physical addressing; how-
ever, any unused address bits must be forced to zero. Otherwise, behavior will be
UNPREDICTABLE.
Figure 1–19 Scatter-Gather PTE Format
The size of the scatter-gather map table is determined by the size of the PCI target
window as defined by the window mask register shown in Table A–14. The number
of entries in the table equals the window size divided by the page size (8KB). The
size of the table is simply the number of entries multiplied by 8 bytes.
The scatter-gather map table address is obtained from the translated base register and
the PCI address as shown in Table A–14.
Table A–14 Scatter-Gather Mapped PCI Target Address Translation
(Sheet 1 of 2)
W_MASK<31:20>
Size of SG
Map Table
Translated Address <32:2>
0000 0000 0000
1KB
Translated Base<33:10>
1
: ad<19:13>
0000 0000 0001
2KB
Translated Base<33:11> : ad<20:13>
0000 0000 0011
4KB
Translated Base<33:12> : ad<21:13>
0000 0000 0111
8KB
Translated Base<33:13> : ad<22:13>
0000 0000 1111
16KB
Translated Base<33:14> : ad<23:13>
63
01
20
21
00
LJ-04275.AI4
PAGE_ADDRESS<32:13>
VALID
MBZ
