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Summary of Contents for Trio64V+

Page 1: ......

Page 2: ...S3 Incorporated Trio64V Integrated Graphics Video Accelerator Trio64V Integrated Graphics Video Accelerator July 1995 S3 Incorporated 2770 San Tomas Expressway Santa Clara CA 95051 0968...

Page 3: ...tion may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying or otherwise without the prior written consent of S3 Incorporated 2770...

Page 4: ...VL BUS INTERFACE 6 6 6 2 1 VL Bus Cycles 6 6 6 2 2 SRDY Generation 6 6 Section 7 Display Memory 7 1 7 1 DISPLAY MEMORY CONFIGURATIONS 7 1 7 2 DISPLAY MEMORY REFRESH 7 4 7 3 DISPLAY MEMORY FUNCTIONAL T...

Page 5: ...13 1 13 2 REGISTER ACCESS 13 2 13 2 1 Unlocking the S3 Registers 13 2 13 2 2 Locking the S3 Registers 13 3 13 2 3 Unlocking Locking Other Registers 13 3 iv 13 3 TESTING FOR THE PRESENCE OF A Trio64V C...

Page 6: ...s Register Descriptions 20 1 Section 21 Streams Processor Register Descriptions 21 1 Section 22 LPB Register Descriptions 22 1 Section 23 PCI Register Descriptions 23 1 Appendix A Register Reference A...

Page 7: ...e 7 10 Internal RAMDAC Block Diagram 8 1 PLL Block Diagram 9 2 Streams Processor 10 1 Screen Definition Parameters 10 5 LPB Internal Block Diagram 11 1 Trio64V to Scenic MX2 Hardware Interface 11 2 11...

Page 8: ...Incorporated Title Page 12 9 VAFC Implementation 32 bit PO Bus 12 8 12 10 VAFC Implementation 64 bit PO Bus 12 8 12 11 Pass Thru Feature Connector 32 bit PO 12 9 12 12 Pass Thru Feature Connector 64...

Page 9: ...Tri064V 4 9 Reset Timing 4 10 Definition of PD 28 0 at the Rising Edge of the Reset Signal 5 2 VL Bus Upper Address Decoding 6 6 Memory Size Chip Count Configurations Tri064V Color Modes PLL R Parame...

Page 10: ...accelerated MPEG 1 video playback Game and Presentation Effects Hardware double buffering support for high quality tear free playback 2 D scrolling and sprite plane support Color and chroma keying fo...

Page 11: ...video digitizers to attain full mo tion video 1 2 S3 STREAMS PROCESSOR The S3 Streams Processor allows the mixing of three separate display streams The primary stream can be RGB data of any color dept...

Page 12: ...Tri064V operates in LPB mode In compatible mode the physical and functional characteristics of the Tri064V are the same as described for the Tri064 in the Trio32 Trio64 Graphics Accelerators Data Book...

Page 13: ...lowing Trio64 features are not available in LPB mode Genlocking Shared frame buffer support Direct decoding of the VL Bus SA 31 23 lines Two SAUP inputs provide indirect decoding via external logic 4...

Page 14: ...1 THERMAL SPECIFICATIONS Parameter Min Typ Max Unit Thermal Resistance 0JC 5 C W Thermal Resistance 0JA Still Air 24 C W Junction Temperature 125 C 2 2 MECHANICAL DIMENSIONS The Trio64V comes in a 20...

Page 15: ...Graphics Video Accelerator S3 Incorporated 30 60 0 30 29 60 0 20 28 80 0 50 0 10 LINEAR DIMENSIONS ARE IN MILLIMETERS 0 20 0 08 11 0 50 0 20 Figure 2 1 20S pin PQFP Mechanical Dimensions 2 2 MECHANIC...

Page 16: ...tions These modes are selected according to the strapping of the PD24 pin at power on reset If PD24 is strapped low at reset the Trio64V powers up in Local Peripheral Bus LPB mode This mode is not pin...

Page 17: ...B MODE lD81 TOP VIEW LD9JPA9IH01 MA2 LD101PA101HD2 MAS LD111PA111HD3 MA3 LOl21PA121HD4 MA4 GOP1 vss iCANK POOt von PDl6lGOO FiEill PD30 SClK PD17 GD VSS PD29 velKI PDt8 GOZ RESERVE FOR PCI GN PD28 RES...

Page 18: ...SA7 MA8 LPB MODE L TOP VIEW SA11 MA2 SA12 MAS SA13 MA3 SA14 MA4 SAlS VSS SAt6 P031 VOO PDt6 SRrSH P030 SClK PDt7 VSS P029 SAt7 POtS SAtS P02S SA11 POtl SA20 VDD SA2t P027 SA22 VSS lD71PA7 PD20 V REOiv...

Page 19: ...CI Multiplexed Address Data Bus A bus transaction 10 11 13 18 cycle consists of an address phase followed by one 28 31 33 36 or more data phases 39 46 SD 31 0 B VL System Data Bus SA 22 2 I 201 196 19...

Page 20: ...ycle Indicator This signal is output during local bus cycles to allow system logic chip sets to prevent concurrent EISA ISA cycle generation IDSEL I 8 PCI Initialization Device Select This input is th...

Page 21: ...nly used for test purposes XOUT 0 157 Crystal Output If an external 14 318 MHz crystal is used it is connected between XIN and this pin This pin drives the crystal via an internal oscillator DISPLAY M...

Page 22: ...it PD bus operation If the Tri064 compatible VAFC feature connector is enabled bit 0 of SRD set to 1 and bit 1 of SRD cleared to 0 OEl is held high not asserted This ensures that EDO memory data is no...

Page 23: ...n ESYNC is high HSYNC VSYNC and BLANK become outputs EVIDEO I 203 External Video The EVIDEO function is on pin 203 when LPB feature connector operation is enabled It is VFCEVIDEO I 111 on pin 111 when...

Page 24: ...rts GA 15 0 0 105 103 101 PCI General Address Bus These signals provide the 98 95 93 91 address for BIOS ROM reads They are multiplexed 89 88 90 92 with PD signals Programmers must ensure that the 94...

Page 25: ...is programmed via MMFF20_1 As an input its status is read via MMFF20_3 In either case the serial port must be enabled by setting MMFF203 to 1 PD 26 25 can be strapped to allow I O E2H or E8H access t...

Page 26: ...LD 7 0J I 202 184 175 LPB Data Bus 7 0 This is the Scenic Highway data 174 155 154 bus and carries video data input 147 146 OS 179 Data Strobe The Trio64V asserts this signal to select the CL 480 for...

Page 27: ...168 168 AVDD 164 169 170 164 169 170 AVSS 159 161 163 167 173 15 161 16a 167 173 BLANK 191 206 CAS 3 0J 82 83 85 86 82 83 85 86 CAS 7 4J 52 51 49 48 52 51 49 48 C BE 3 0J 7 19 27 38 CLKAVDD l 2J 158 1...

Page 28: ...128 144 142 140 13 134 132 13 12a 127 129 131 133 136 139 141 143 127 129 131 133 136 139 141 143 70 68 66 64 61 58 56 54 53 55 70 68 66 64 61 58 56 54 53 55 57 59 63 65 67 69 105 103 101 57 59 63 65...

Page 29: ...142 140 138 134 132 130 128 144 142 140 138 134 132 130 128 127 129 131 133 136 139 141 143 127 129 131 133 136 139 141 143 VFCVCLK 117 117 VFCVCLKI 106 106 VCLK 148 148 VCLKI 106 106 VDD 12 37 62 81...

Page 30: ...A023 S023 11 A022 S022 12 VDD VDD 13 A021 S021 14 A020 S020 15 A019 S019 16 A018 S018 17 A017 S017 18 A016 S016 19 C BE2 SBE2 20 FRAME SAOS 21 IROY ROYIN 22 VSS VSS 23 TROY SROY 24 OEVSEL LOCA 25 STO...

Page 31: ...S7 CAS7 53 PD23 GD7 PD23 54 PD24 PD24 55 PD22 GD6 PD22 56 PD25 PD25 57 PD21 GD5 PD21 58 PD26 PD26 59 PD20 GD4 PD20 60 VSS VSS 61 PD27 PD27 62 VDD VDD 63 PD19 GD3 PD19 64 PD28 PD28 65 PD18 GD2 PD18 66...

Page 32: ...12 GA12 PD12 99 VSS VSS 100 PD2 GA2 PD2 101 PD13 GA13 PD13 102 PD1 GAl PDl 103 PD14 GA15 PD14 104 PDO GAO PDO 105 PD15 GA15 PD15 106 PD55NFCVCLKI PD55NFCVCLKI 107 PD56 PD56 108 PD54 PD54 109 PD57NFCES...

Page 33: ...PA12 PD44NFCPA12 139 PD34NFCPA2 PD34NFCPA2 140 PD45NFCPA13 PD45NFCPA13 141 PD33NFCPA1 PD33NFCPA1 142 PD46NFCPA14 PD46NFCPA14 143 PD32NFCPAO PD32NFCPAO 144 PD47NFCPA15 PD47NFCPA15 145 VSS VSS 146 LDO P...

Page 34: ...LD6 PA6 LD6 PD6 185 LD8 PA8 HDO SA10 186 LD9 PA9 HDl SAll 187 LDl O PA10 HD2 SA12 188 LDll PA11 HD3 SA13 189 LD12 PA12 HD4 SA14 190 STWR GOPl SA15 191 BLANK SA16 192 VDD VDD 193 RESET SRESET 194 SCLK...

Page 35: ...r Trio64V Integrated Graphics Video Accelerator 53 Incorporated...

Page 36: ...70 C Table 4 2 RAMDAC Clock Synthesizer DC Specifications Symbol Parameter Min Typical Max Unit AVDD DAC supply voltage 4 75 5 5 25 V AVDD CLOCK PLL supply voltage 4 75 5 5 25 V VREF Internal voltage...

Page 37: ...Current 1 IlA CIN Input Capacitance 5 pF COUT Output Capacitance 5 pF Icc Power Supply Current 500 Note 5 mA Notes for Table 4 4 1 The value for pins 25 STOP and 26 PAR is 2 6V 2 IOL1 IOHl for pins R...

Page 38: ...RAMDAC AC Specifications Parameter Typical Max Unit Notes DAC Output Delay 5 ns 1 DAC Output Rise Fall Time 3 ns 2 DAC Output Settlinq Time 15 ns DAC to DAC Output Skew 2 5 ns 3 Notes for Table 4 5 1...

Page 39: ...SCLK High Time VL Bus 8 80 ns SCLK High Time PCI 12 80 ns LCLK High Time 12 160 ns TLOW SCLK Low Time VL Bus 8 80 ns SCLK Low Time PCI 12 80 ns LCLK Low Time 12 160 ns SCLK Slew Rate 1 4 V ns 3 LCLK...

Page 40: ...L hold 1 ns VL Bus Symbol Parameter Min Units Tsu AO 31 2 BE 3 0 SM IO SW R SAOS address 12 ns phase setup TH AO 31 2 BE 3 0 SM IO SW R SAOS address 1 ns phase hold Tsu AO 31 2 BE 3 0 01 00 SAOS data...

Page 41: ...rface Symbol Parameter Min Units Tsu LD 7 0 setup also LD 15 8 for 16 bit interface 6 ns TH LD 7 0 hold also LD 15 8 for 16 bit interface 8 ns Tsu HS setup 6 ns TH HS hold 7 ns Tsu VS setup 6 ns TH VS...

Page 42: ...es AD 31 OJ valid delay 2 16 ns 1 DEVSEL PAR 2 11 ns Medium DEVSEL delay timing used STOP delay 2 11 ns TRDY delay 2 11 ns INTAdeiay 2 11 ns VL Bus Parameter Min Max Units Notes AD 31 21 D1 DO valid d...

Page 43: ...active delay 1 6 5 ns OE l OJ active delay 1 5 4 5 ns WE active delay 1 5 4 5 ns Note 1 The maximum delay time is 7 ns for l cycle operation and 11 ns for 2 cycle operation Table 4 13 CL 480 Timings T...

Page 44: ...ld from VCLK or 6 ns 1 VCLKI rising VCLK 25 40 ns 1 VCLKI 27 40 ns 1 2 VCLK VCLKI duty cycle 40 60 VCLK VCLKI high time 10 25 ns VCLK VCLKI low time 10 25 ns VCLK VCLKI slew rate 1 4 V ns Notes for Ta...

Page 45: ...ATION DATA Figure 4 4 Reset Timing Table 4 16 Reset Timing Symbol Parameter TLQW SRESET VL or RESET PCI active pulse width Tsu PD 28 0 setup to SRESET Vl or RESET PCI inactive TH PD 28 0 hold from SRE...

Page 46: ...reset At the rising edge of the reset signal this state is sampled and the data loaded into the CR36 CR37 CR68 and CR6F reg isters The data is used for system configuration such as system bus and mem...

Page 47: ...BIOS accesses 1 Enable video BIOS accesses Display Memory Size CR36 7 5 7 5 000 4 MBytes 001 Reserved 010 Reserved 011 Reserved 100 2 MBytes 101 Reserved 110 1 MByte 111 Reserved Enable Tri064V IVL Bu...

Page 48: ...r use by the video BIOS Memory Data Bus Size CR687 23 0 Memory data bus is 32 bits 1 Memory data bus is 32 bits 1 MByte or 64 bits 2 or more MBytes Operating Mode Select CR6F 0 24 0 LPB mode 1 Trio64...

Page 49: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated...

Page 50: ...PCI configu ration it defaults to linear addressing and mem ory mapped I O enabled at a relocatable base address of 7000 OOOOH This allows the PCI sys tem to reconfigure as required for plug and play...

Page 51: ...I I I I I I I I TROY I I I I I I I I _ I I I I I OEVSEL I I I I I I I I BASEREAD Figure 6 1 Basic PCI Read Cycle T1 T2 T3 T4 T5 T6 SCLK 1 FRAME I 1 AD 31 0 AOO ESS I DATA 1 OAlA2 X DAlA3 o 1 1 1 1 C B...

Page 52: ...ted T1 T2 T3 T4 SCLK FRAME I I I IRDY TROY I I I I STOP I cds I I I DEVSEL I I I I SCLK I I r I DISCONA Figure 6 3 PCI Disconnect Example A T1 T2 T3 T4 i7 I I I STOP I I I I I I I DEVSEL i DISCONB Fig...

Page 53: ...BE S i r r 0 r i __ 11 I 0 t i r l I I I I C GREAD Figure 6 6 PCI Configuration Read Cycle T1 T2 T3 T4 SCLK I I I I I I I I t I x I FRAME I I I I I I I I I AD 31 0 ADDRrSS X D A I I I I I IDSEL_ I I I...

Page 54: ...Tl SCLK I I FRAME l I I I I I AD 31 0 I I ADDRfSS I I I I PAR I l 9 I Figure 6 7 Read Parity Operation The Trio64V drives even parity information onto the PAR line during read transactions This op er...

Page 55: ...two rising SCLK edges as shown in Figure 6 8 and explained in Note 1 The basic VL Bus write cycle is shown in Figure 6 9 The single wait state is the default configu ration This can be changed to 0 wa...

Page 56: ...le Notes 1 For one decode wait state bit 4 of CR40 set to 1 the address is latched on the first clock edge in dicated here if bit 3 of CR58 is set to 1 If this bit is cleared to 0 the address is latch...

Page 57: ...is latched on the first clock edge in dicated here if bit 3 of CR58 is set to 1 If this bit is cleared to 0 the address is latched on the second clock edge indicated The address is always latched on t...

Page 58: ...32 bits This reduces performance and the number of video modes available as compared with 64 bit PO bus operation Tri064 compatible VAFC feature con nector operation can be enabled SRD_1 O The configu...

Page 59: ...to 4 MBytes If feature connector operation is never required OEO pin 124 can be used to drive both the 1st and 2nd MBytes of both fast page and EDO DRAM configurations This configuration can be upgra...

Page 60: ...PO 63 O MAla o I256Kx16 IPD 63 48 RASO CAS6 CAS7 WE RAM CONTROL PCI CONRGURATtoNSONLY ANDSRA_6 1 PIN 50 RAS1 PO 5 O I 256 6 IPO 31 6 PO 47 321 256Kx16 I PD 63 48 RAS1 CAS6 CAS7 WE 4M 1FP 1 1 w n o 1 i...

Page 61: ...ead cycle This also shows how certain parameters for various control signals can be adjusted to meet the access time require T6 T7 T8 T9 T10 r SEE NOTE 2 r 1 LATCHING I YD r r j I SEE NOT 3 MA 8 0j __...

Page 62: ...via bits 4 3 of CR6F Figure 7 5 shows the functional timing for a fast page mode read modify write cycle This is a 1 wait state cycle T6 T7 T8 T9 T10 SEE NOTE 1 r SEE NOTE 2 1 _ MA 8 0 ___ R_O_W ___...

Page 63: ...eo Accelerator 3 Incorporated T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 MCLK ____________ r LJ gJ ___R_O_W ___ JX COLUMN l i I COLUMN Ii LJ WE f VTx PD 63 0 WRITEDATA N1 FPRMW Figure 7 5 Fast Page Mode Read Modi...

Page 64: ...s for RAS and for CAS OENIE as described above for a fast page mode read cycle als ly to EDO cycles Note that if the minimum RAS active time is specified T6 T7 T8 T9 T10 SEE NOTE 1 ___________________...

Page 65: ...The cycle depicted in Figure 7 6 is for 64 bit PD bus operation 2 MBytes of memory and feature connector operation disabled If the feature con nector is enabled OEO only enables data output on PD 31...

Page 66: ...to latch the last read Write data is latched by the DRAM on the falling edge of CAS No dummy cycle is required and the last CAS shown in the diagram does not occur T1 T2 T3 T4 MCLK Figure 7 9 shows a...

Page 67: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated T1 T2 T3 T4 T5 T6 T7 T8 T9 MCLK ______ 1 CAS u 11 PD 63 0 SCEDORMW Figure 7 9 1 cycle EDO Read Modify Write Cycle 7 10 DISPLAY MEMORY...

Page 68: ...e for FIFO filling before memory control is given up for M parameter processes Note that this parameter is only effective when both FIFO threshold values are equal to or above the threshold level and...

Page 69: ...Trio64V Integrated Graphics Video Accelerator 53 Incorporated...

Page 70: ...the setting of CR67_3 2 the follow ing operating modes are available Streams Processor Off Streams Processor On Streams Processor On secondary stream overlaid on VGA Mode 13 back ground With the Strea...

Page 71: ...directly to the DACs each pixel clock Each of the 6 color modes is listed in Table 8 1 The desired mode is selected by programming bits 7 4 of CR67 8 2 RAMDAC FUNCTIONALITY Description 8 bit pseudo co...

Page 72: ...iguration space register Index 04H to 1 causes the Tri064V to snoop for RAM DAC writes This means that the Tri064V will write the data to its local RAMDAC but will not claim the cycle by asserting DEV...

Page 73: ...I Trio64V Integrated Graphics Video Accelerator S3 Incorpora ed...

Page 74: ...he programmed value In particular the R value is the code not the actual frequency divisor The PLL M value can be programmed with any integer value from 1to 127 The binary equivalent of this value is...

Page 75: ...SR12 and SR13 The new PLL parameter values can be loaded in one of two 9 2 CLOCK SYNTHESIS AND CONTROL ways If bit 5 ofSR15 is cleared to 0 the new DCLK frequency is loaded by setting bit 1 of SR15 to...

Page 76: ...the internal clock synthe sizer VCLK is the signal used to clock pixel data into the internal RAMDAC For most modes of operation VCLK is generated directly from DCLK and has the same frequency and ph...

Page 77: ...Ii Trio64V Integrated Graphics Video Accelerator 53 Incorporated...

Page 78: ...hin the frame buffer 3 Hardware Cursor 64x64x2 cursor either Microsoft or X 11 definition Regardless of the input formats the Streams Processor creates a composite RGB 24 8 8 8 output to the DACs This...

Page 79: ...data written by the graphics controller such as a sprite used by game programmers for moving objects It could also be RGB YUV or YCbCr data written to the 10 2 STREAMS PROCESSOR frame buffer by some v...

Page 80: ...nput stream OR secondary frame buffer starting address 1 MMS1D4_21 0 used for the secondary stream and LPB frame buffer starting address 1 MMFF10_21 0 used for the LPB input stream Which alternative a...

Page 81: ...e starting address offset in the frame buffer for a second image buffer into which is written data from the LPB The secondary stream can be generated from this buffer MM81CC_6 LPB Input Buffer Select...

Page 82: ...he K2 horizontal factor is 10 25 15 Programming these parameters with these values results in a 2 5x horizontal stretch for the secondary stream window SCREEN START XO 10 3 COMPOSITION OUTPUT A variet...

Page 83: ...fer and is shown as HO in Figure 10 2 The final value is the same height value that is programmed in MM81 FC_10 0 and is shown as H1 in Figure 10 2 This value is then the 2 s complement of H1 HO MM81E...

Page 84: ...list The blender accepts the primary and secondary pixel streams and blends them with an arithmetic weighting The result isthen over laid with the cursor stream Both blender inputs are RGB B B 8 from...

Page 85: ...is YUV or YCbCr the chroma key is specified as a range of color values The lower bound value is defined in MM8184_23 16 The upper bound value is de fined in MM8194_23 0 If the secondary stream pixel c...

Page 86: ...o 8 bit Trio64V in put for VL Bus configurations However the Scenic MX2 has a glueless SAA7100 interface which can be used to provide the 16 to 8 bit conversion A 16 bit data interface is available on...

Page 87: ...EQ CRDY ENABLE this as a write Bit 4 is 1 for a register access and ofor a memory access Bits 3 0 are bits 19 16 of the address The second byte is bits 15 8 of MMFF14 and the third byte is bits 7 0 Th...

Page 88: ...__ 1 VREQNRDY LOl7 _ _ _ _ _ Figure 11 4 Scenic MX2 Write Scenic MX2 Not Ready LCLK CREQ CROY VREQNROY ____________________________ r_ L0 7 0 Figure 11 5 Scenic MX2 Read Scenic MX2 Ready LCLK CREQ CR...

Page 89: ...e FIFO MMFFOO_17 16 are programmed to specify the number of doublewords of data to burst to the Scenic MX2 A write to the output FIFO then initiates a compressed data write to the Scenic MX2 This is d...

Page 90: ...MMFF08_17 to 1 The status is read via bit 1 of this same register 11 1 3 Scenic MX2 Video Capture The following setup is done for Scenic MX2 video capture LCLK CREQ CRDY VSYNC One or two frame buffer...

Page 91: ...ending data three clocks later This is LCLK shown in Figure 11 10 The Tri064V assumes data has begun any time CREO CRDY is held low for more than two cycles When the Scenic MX2 is sending the last byt...

Page 92: ...manner 11 2 DIGITIZER INTERFACE The hardware interface to the Philips digitizer in Video 8 In mode MMFFOO_3 1 010b is shown SAA7110 Y 7 0 UV 7 0 LLC2 LLC HS VS SDA SCK in Figure 11 12 This section de...

Page 93: ...O_3 1 001b for PCI con figurations Byte swapping is disabled by setting MMFFOO_6 to 1 VS I L ss HS 1 m LD 7 OI The correct vertical and horizontal sync polarities are specified MMFFOO_9 10 One or two...

Page 94: ...nected This is shown by the top set of signals in Figure 11 15 The functional timing is Trio64V LO 6 2 L L LO 1 0 L07 HS VS LCLK HO 7 0 oL HSEL 2 0 OS RIW OTACK 1 0 CFLEVEL i L the same as for the SAA...

Page 95: ...e LPB bus The data are sent exactly as for com pressed video data to an MPEG decoder The data will then be decimated according to the programming of MMFF2C horizontal and MMFF30 vertical and then pass...

Page 96: ...178 PCI NO FUNCTION NO FUNCTION HSELO 179 PCI NO FUNCTION NO FUNCTION DS 180 PCI NO FUNCTION NO FUNCTION RMJ 181 PCI NO FUNCTION NO FUNCTION DTACK 182 PCI NO FUNCTION NO FUNCTION CFLEVEL 184 LD6 LD6...

Page 97: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated...

Page 98: ...n then power on Trio64V GO 7 0 GA 15 0 ROMEN strapping bit 4 CR36 bit 4 must be pulled low to disable BIOS accesses For this configuration ROMCS is not required Bits 1 0 of SR1C can be set to 11 makin...

Page 99: ...ds as defined by the states of the byte en ables For a 16 bit read the Tri064V automat ically increments the lower address once and generates the second byte of read data For a 12 2 MISCELLANEOUS FUNC...

Page 100: ...II S3 Incorporated I J en c o II 0 w 2 C C Trio64V Integrated Graphics Video Accelerator I I II z i J en Ii s Cl s IS c Cl Figure 12 3 BIOS ROM Read Functional Timing PCI MISCELLANEOUS FUNCTIONS 12 3...

Page 101: ...General Input Port GIP for PCI configurations as part of its LPB VE5A LOCAL BU5 50 7 0 Q 7 0 GENERAL function The following steps are required to implement it 1 Disable all other LPB uses 2 Enable dr...

Page 102: ...shown in Figure 12 5 The entire cycle from assertion of SADS to data being avail able on SD 7 0 takes approximately 18 20 SCLKs T1 DCLK 12 4 GENERAL OUTPUT PORT The Tri064V provides a 4 bit General O...

Page 103: ...tes as long as SR1C_1 1 The values in CR5C_1 0 can be repro grammed at any time The Tri064V provides an 8 bit GOP for VL Bus configurations The block diagram this configu ration is shown in Figure 12...

Page 104: ...signals are multiplexed on upper PO lines The pins used to provide this type of operation are listed in Table 12 1 Table 12 1 Trio64 compatible Feature Connector Configuration Pin s Sianals 144 142 1...

Page 105: ...VSYNC VSYNC BLANK BLANK EVIOEO EVIOEO ESYNC GROY EVCLK 5V 5V 5V 5V TVVAFCl Figure 12 9 VAFC Implementation 32 bit PO Bus 245 Trio64V VAFC 64 BIT PO BUS PA 15 0 PA 15 0 ENFEAT VCLKI VCLK VCLK OCLK HSYN...

Page 106: ...BLANK BLANK EVIOEO EVIOEO ESYNC ESYNC EVCLK EVCLK TPASCON1 Figure 12 11 Pass Thru Feature Connector 32 bit PO Trio64V PASS 64 BIT PO BUS THROUGH PA 7 0 245 PA 7 0 ENFEAT G DIR VCLK VCLK HSYNC HSYNC V...

Page 107: ...r VAFC or pass through bidirectional feature connector In all cases SRO_O must be set to 1 to enable feature connector operation and SR1C_1 0 must be OOb to enable ENFEAT on pin 151 ln addition LPB op...

Page 108: ...rs of lines based on two select signals Each side can act as either an input or output A set of schematics showing the use of this part is available For PCI LPB configurations SPCLK and SPD are not mu...

Page 109: ...r 53 Incorporated Trio64V Integrated Graphics Video Accelerator remain asserted until all interrupt status bits are cleared 12 12 MISCELLANEOUS FUNCTIONS...

Page 110: ...Trio64V This is required for systems that do not use the S3 style of video BIOS e g UNIX mov dX 3c3h mov aI 01h out dX al load CRTCs mov dX 3C6h mov al FFh out dX al Video Subsystem Enable register a...

Page 111: ...re the index register address to dx Write code to CR39 to provide access to the System Control and System Extension registers CR40 CRFF dx is already loaded with 3D4h because of the previous instructi...

Page 112: ...ess read content of CR40 into al clear bit 0 to 0 write to CR40 to lock the Enhanced Commands registers restore the index register address to dx 13 2 3 Unlocking Locking Other Registers The Extended S...

Page 113: ...index to index register increment dx to 3D5h data register address read content of CR2F into al mask out all but bit 6 compare chip revision to the desired chip revision 4xh jump to a label if revisio...

Page 114: ...access to this register Bit 7 of CR43 doubles the parameter size CR3 The length of the blanking pulse defined in this register can be extended by 64 DCLKs via bit 3 of CR5D Bit 5 of CR35 controls acc...

Page 115: ...register CR15 In addition to the standard VGA extensions bit 8 is bit 3 of CR7 bit 9 is bit 5 of CR9 bit 10 is bit 2 of CR5E Bit 4 of CR35 controls access to this register CR16 Bit 4 of CR35 controls...

Page 116: ...re linear addressing is enabled This means that bit 0 of 4AE8H is set to 1to enable Enhanced mode functions and bit 3 of CR31 is setto 1to specify Enhanced mode memory mapping The Tri064V provides lin...

Page 117: ...ed by the SRC NE source not equal bit bit 7 of BEE8H Index OEH If this bit is 0 the new pixel color value is passed to the write mask only when the source color does not match the color in the Color C...

Page 118: ...SRC NE COLOR COMP FALSE Trio64V Integrated Graphics Video Accelerator COLOR COMPARE MASK BIT SOURCE COLOR SOURCE B NO SRC NE COLOR COMP TRUE SRC NE 0 COLOR COMP FALSE NEW PIXEL COLOR PIXUPDT Figure 15...

Page 119: ...er AAE8H is set up to indicate the active planes When all bits of the read enabled planes for a pixel are a 1 the mask bit ONE is generated If anyone of the read enabled planes is a 0 then a mask bit...

Page 120: ...EAD SEL BEE8 E BEE8 F 8144 MIN AXIS PCNT MAJ AXIS PCNT BEE8 0 96E8 ALT PCNT 8148 814A PIX TRANS E2E8 E2EA PIX TRANS For improved performance most of the Enhanced mode registers can also be written but...

Page 121: ...hen bits 4 3 of CR53 are set to 11b This is the default for a PCI bus configuration allowing PCI software immediate access to all registers and the ability to relocate the address space VL Bus configu...

Page 122: ...x value in the high word I e 31 15 0 EAX I X Y I MOV ES ALT_CURXY1 EAX The packed register MMIO scheme is the most efficient and is used where appropriate in the programming examples provided later in...

Page 123: ...ALSE comparison allows the pixel update to continue The comparison color is programmed into the Color Compare register B2E8 All planes are enabled for writing unless explicitly set otherwise in an exa...

Page 124: ...he V drawing direction is positive y1 y2 Clearing bit 7 to 0 means the V drawing direction is negative y1 y2 Setting bit 6 to 1 means that V is the major longer axis ABS x2 x1 ABS y2 y1 Clearing bit 6...

Page 125: ...parameters and registers used in this example 3 1_______1 5_______0 ES ALT_MIX IL _0_0_27_H_ 0_0_05_H l1 FRGD_COLOR is color source and NEW is mix BKGD_COLOR is color source and XOR is mix ES FRGD_COL...

Page 126: ...line will vary from 0 to n 1 where n is the transfer width in bits With a transfer width of 8 bits the number of byte writes required per line can be determined from the formula n MAX 7 8 with n being...

Page 127: ...TL AOOOH Drawing Operation color source is FRGD_COLOR NEW mix type color index FRGD_MIX specifies the color source and mix type 31 15 0 ES ALT_CURXY L _ _ x_1_ L_ y_1_ l set starting coordinates 31 15...

Page 128: ...ll bit 9 of 9AE8H register is 0 Draw rectangle bits 15 13 11 swap ON bit 12 32 bit transfers bits 10 9 wait for CPU data bit 8 always X Major bit 6 X Positive bit 5 draw bit 4 COUNT of image pixel dat...

Page 129: ...UNT W 1 2 H words 32 bit transfers COUNT W 3 4 H dwords COUNT for 16 bits pixel modes 8 bit transfers Do not use this combination 16 bit transfers COUNT W H words 32 bit transfers COUNT W 1 2 H dwords...

Page 130: ...bit bus width Setup 31 15 0 r I 1 ES ALT_MIX 0027H 0005H L ______ ______ FRGD_COLOR color source and mix is NEW ES FRGD_COLOR 00000004H ES BKGD_COLOR OOOOOOOOH ES PIXEL_CNTL A080H Drawing Operation BK...

Page 131: ...COUNT W 7 B H 3 4 dwords 9AEBH_10 9 11b Tri032 only The differences between the two 32 bit transfer options are 1 For 9AEBH_10 9 set to 10b every line of the transfer must start with a fresh doublewo...

Page 132: ...being copied are HEIGHT and WIDTH Setup First the values of the Srcx Srcy Destx and Desty must be determined Case 1 Source and destination rectangles do not overlap For X Positive Y Positive Srcx x1 S...

Page 133: ...a 1 a 1 is copied as specified by the foreground mix When the bit read is a 0 a 0 is copied as specified by the background mix Assume x1 y1 is the top left corner of the source rectangle on the displa...

Page 134: ...ory into a 2 color image This is accomplished by setting the mix registers differently and setting the desired background and foreground colors If the source bit is a 1 then the corresponding pixel at...

Page 135: ...H to select the Foreground Mix register to specify the color source and mix type The color source must be specified as the bitmap display memory Bit 6 ofthe Command register must be setto 1to specify...

Page 136: ...is a 0 a 0 is copied as specified by the background mix In this example assume x1 y1 is the top left corner of the pixel pattern and x2 y2 is the top left corner of the destination rectangle The image...

Page 137: ...ine the direction with bit 4 set to 1 for a draw operation or to 0 for a move current position operation Bits 3 0 define the length of the short line Let SSVDO SSVD1 SSVDN 1 bytes be the short stroke...

Page 138: ...can be enabled or disabled when in Enhanced mode bit 0 of 4AE8H 1 as follows CR39 AOH CR45_0 1 CR45_0 0 CR39 OOH Positioning the Cursor Unlock System Control registers Enable hardware cursor Disable...

Page 139: ...yte segment CR39 0 Lock System Control registers The value programmed is the 1024 byte segment of display memory at which the beginning of the hardware cursor bit pattern is located For example for an...

Page 140: ...a table listing each register in this section and its page number 16 1 GENERAL REGISTERS This section describes general input status and output control registers Miscellaneous Output Register MiSe Wr...

Page 141: ...ct the high 64K page of memory Bit 6 HSP Select Negative Horizontal Sync Pulse o Select a positive horizontal retrace sync pulse 1 Select a negative horizontal retrace sync pulse Bit 7 VSP Select Nega...

Page 142: ...rupt Status 0 Vertical retrace interrupt cleared 1 Vertical retrace interrupt pending See Section 12 7 for an explanation of interrupt generation Input Status 1 Register STATUS_1 Read Only Address 3 A...

Page 143: ...ected to two of the eight color outputs of the attribute controller Bits 5 and 4 of the color plane enable register AR12 control the multi plexer for this video output observation Bits 7 6 Reserved Vi...

Page 144: ...r is loaded with a binary value that indexes the sequencer register for read write data This value is referred to as the Index Number of the SR register in this document 7 6 5 4 3 2 1 o R R R SEQ ADDR...

Page 145: ...haracter clock 7 0 6 5 4 3 2 1 0 SCRN SHF DCK SHF 0 OFF 4 1 2 LD 0 80C Bit 0 80C 8 Dot Clock Select o Character clocks 9 dots wide are generated 1 Character clocks 8 dots wide are generated Bit 1 Rese...

Page 146: ...N_WT_PL SR2 Read Write Address 3C5H Index 02H Power On Default OOH This register selects write protection or write permission for CPU write access into video memory 3 2 1 o EN wT PL Bits 3 0 EN WT PL...

Page 147: ...ble 256 KBytes of video memory support 8 character sets This register is reset to 0 asynchronously during a system reset Bits 4 1 0 SLB Select Font B This value selects the portion of plane 2 used to...

Page 148: ...his bit affects only CPU write data accesses into video memory Bit 3 of this register must be 0 for this bit to be effective o Enables the odd even addressing mode Even addresses access planes 0 and 2...

Page 149: ...equencer 9 Register SR9 Read Write Address 3C5H Index 09H Power On Default OOH 6 I I I I I R I I R Bits 6 0 Reserved Bit 7 MMIO ONLY Memory mapped I O register access only 0 When MMIO is enabled both...

Page 150: ...ry This setting should always and only be used for 4 MByte configurations Tri064 compatible VAFC feature connector operation cannot be used with this setting and should never be enabled Bit 7 2MCLK 2...

Page 151: ...ides feature connector control and also provides independent control of the HSYNC and VSYNC signals therefore supporting the VESA DPMS Display Power Management Con trol standard 7 I 6 5 I 4 3 2 1 0 VS...

Page 152: ...wer on default value for SR11 generate an MCLK value of 45 MHz All other MCLK values must be specified by programming of SR10 and SR11 Loading of a new value is enabled by either bit 0 or bit 5 of SR1...

Page 153: ...ription below The power on default value for this register in conjunction with the power on default value for SR13 generate a DCLK value of 25 175 MHz The default value is automatically placed in this...

Page 154: ...automatically placed in this register when bits 3 2 of 3C2H are programmed to OOb If bits 3 2 of CR2H are programmed to alb the ap propriate PLL M value for a 28 322 MHz DCLK will automatically be pl...

Page 155: ...r counters This bit is used for S3 test purposes only Bit5 P151 SEL Pin 151 function select 0 Pin 151 functions normally 1 Pin 151 is tri stated Setting this bit to 1 allows pin 151 to act as an MCLK...

Page 156: ...an be set to 1 to load these values in the PLL Bits 3 2 of 3C2H must also be set to 11b ifthey are not already at this value The loading may be delayed a small but variable amount of time This bit sho...

Page 157: ...er must be set to 1 for clock doubled RAMDAC op eration mode 0001 Bit 7 2 CYC MWR Enable 2 cycle memory write o 3 MCLK memory write 1 2 MCLK memory write Setting th is bit to 1 bypasses the VGA logic...

Page 158: ...or S3 test purposes only Bit 2 TST RED Test red data 0 No effect 1 Place red data on internal data bus This bit is used for S3 test purposes only Bit 3 TST GRN Test green data 0 No effect 1 Place gree...

Page 159: ...4 3 2 1 0 R R R R R SIGSEL Bits 1 0 SIGSEL Signal Select For VL 00 Pin 151 is ENFEAT pin 153 is ROMCS 01 Pin 151 is GPIOSTR pin 153 is ROMCS 10 Pin 151 is GOPO pin 153 is ROMCS 11 Pin 151 is GOPO pin...

Page 160: ...Default OOH This register is loaded with a binary value that indexes the CRT controller register where data is to be accessed This value is referred to as the Index Number of the CR register CROO 18 T...

Page 161: ...3 2 o HORIZONTAL TOTAL Bits 7 0 HORIZONTAL TOTAL 9 bit Value number of character clocks in one scan line 5 This register contains the least significant 8 bits of this value Horizontal Display End Regi...

Page 162: ...ch time horizontal blanking ends To obtain this value add the desired BLANK pulse width in character clocks to the Start Horizontal Blank value which is also in character clocks The 5 least significan...

Page 163: ...Bits 4 0 END HORIZONTAL SYNC POS 6 bit Value 6 least significant bits of the character clock counter value at which time HSYNC becomes inactive To obtain this value add the desired HSYNC pulse width i...

Page 164: ...ains the least significant 8 bits of this value CRTC Overflow Register OVFL_REG CR7 Read Write Address 3 5H Index 07H Power On Default Undefined 7 6 5 4 3 2 1 0 VRS VDE VT LCM SVB VRS VDE VT 9 9 9 8 8...

Page 165: ...of bytes to pan The number of pixels to pan is specified in AR13 Bit 7 Reserved 0 Maximum Scan Line Register MA CS_LN CR9 Read Write Address 3 5H Index 09H Power On Default Undefined This register spe...

Page 166: ...egister CESL CRB Read Write Address 375H Index OBH Power On Default Undefined This register defines the row scan of a character line where the cursor ends 7 6 I 5 4 I 3 I 2 I 1 I 0 CSR SKW 0 1 0 CURSO...

Page 167: ...t Undefined 7 6 5 4 3 2 o DISPLAY START ADDRESS LOW Start address low contains the 8 low order bits of the address Cursor Location Address High Register CLA H CRE Read Write Address 3 5H Index OEH Pow...

Page 168: ...units to the CR10 value also in scan line units The 41east significant bits of this sum are pro grammed into this field This allows a maximum VSYNC pulse width of 15 scan line units Bit 4 CLR VINT Cle...

Page 169: ...the scan line where the display on the screen ends Bit 8 and Bit 9 are bits 1 and 6 of CR7 Bit 10 is bit 1 of CR5E 7 6 5 4 3 2 o VERTICAL DISPLAY END Bit 7 0 VERTICAL DISPLAY END 11 bit Value number o...

Page 170: ...address counter depends on bit 3 of CR17 count by 2 1 The memory address counter is incremented every four character clocks The CNT BY4 bit is used when double word addresses are used Bit 6 DBLWD MODE...

Page 171: ...ster is a multifunction control register with each bit defining a different specification 7 RST 6 5 4 3 2 1 0 BYTE ADW WRD VT 4BK 2BK MODE 16K 0 MODE X2 HGC CGA Bit 0 2BK CGA Select Bank 2 Mode for CG...

Page 172: ...hen word mode is selected by bit 6 of this register memory address counter bit 13 appears on the memory address output bit 0 signal of the CRT controller and the video memory address wraps around at 1...

Page 173: ...s determined by the addition of the Offset CR13 register content Bit 8 is bit 4 of CR7 Bit 9 is bit 6 of CR9 Bit 10 is bit 6 of CR5E 7 6 5 4 3 2 o LINE COMPARE POSITION Bit 7 0 LINE COMPARE POSITION 1...

Page 174: ...oller Index register and its associated internal address flip flop AFF It can be read at either index 24H or 26H Bits 4 0 ATTRIBUTE CONTROLLER INDEX This value is the Attribute Controller Index Data a...

Page 175: ...phics controller register will be accessed This value is referred to as the Index Number of the GR register GRO 6 6 3 2 1 0 0 GR CONT ADDRESS Bits 3 0 GR CONT ADDRESS Graphics Controller Register Inde...

Page 176: ...enabled on the corresponding bit of the Enable Set Reset Data register In write mode 3 there is no effect on the Enable Set Reset Data register Bits 7 4 Reserved 0 Enable Set Reset Data Register EN_S...

Page 177: ...pixel Each of the 8 bit positions of the read data are compared across four planes and a logical 1 is returned in each bit position for which the colors match Bits 7 4 Reserved 0 Raster Operation Rot...

Page 178: ...ster is applied to data being written to mem ory while in modes 0 2 and 3 Bits 7 5 Reserved 0 Read Plane Select Register RD_PL_SL GR4 Read Write Address 3CFH Index 04H Power On Default Undefined I I I...

Page 179: ...en to memory plane o The data on the CPU data bus is treated as the color value The Bit Mask register is effective as the Mask register A logical 1 in the Bit Mask register sets the corresponding pixe...

Page 180: ...HF MODE Select 256 Color Shift Mode 0 Bit 5 in this register controls operation of the video shift registers 1 The shift registers are loaded in a manner that supports the 256 color mode Bit 7 Reserve...

Page 181: ...on t care plane when the CPU read from the video memory is performed in read mode 1 1 The corresponding color plane is used for color comparison with the data in the Color Compare register Bits 7 4 Re...

Page 182: ...ex register is read at 3COH and the Attribute Controller Data register is read at address 3C1 H Attribute Controller Index Register ATR_AD Read Write Address 3COH Power On Default Undefined This regis...

Page 183: ...er register indexed by the attribute controller address Palette Registers PLT_REG AROO OF Read Write Address 3C1 H 3COH Index OOH OFH Power On Default Undefined These are 16 6 bit registers pointed to...

Page 184: ...ing o Selects the background intensity for the text attribute intJut 1 Selects blink attribute in text modes This bit must also be set to 1 for blinking graphics modes The blinking counter is op erate...

Page 185: ...dex 11H Power On Default OOH 7 6 5 4 3 2 o BORDER COLOR Bits 7 0 Border Color This 8 bit register determines the border color displayed on the CRT screen The border is an area around the screen displa...

Page 186: ...le in both text and graphics modes It is not available with Enhanced mode memory mappings CR3L3 1 6 5 4 3 2 1 0 0 0 0 NUMBER OF PAN SHIFT Bits 3 0 NUMBER OF PAN SHIFT This register selects the number...

Page 187: ...6 color mode 7 6 5 4 3 I 2 I 1 I 0 PIXEL PADDING 0 0 0 0 V7 V6 V5 V4 Bits 1 0 PIXEL PADDING V5 V4 These bits are enabled with a logical 1 of bit 7 of AR10 and can be used in place of the V5 and V4 bit...

Page 188: ...tte data registers and is used when reading the color palette 7 6 5 4 3 2 o DAC READ ADDRESS Bits 7 0 DAC READ ADDRESS Each time the color code is written to this register it identifies that a read se...

Page 189: ...Register DAC_WR_ADI Read Write Address 3CSH Power On Default Undefined Bits 7 0 DAC WRITE ADDRESS GIP READ DATA This register contains the pointer to one of 256 palette data registers and is used dur...

Page 190: ...gister DAC_DATAI Read Write Address 3C9H Power On Default Undefined This register is a data port to read or write the contents of the location in the color look up table pointed to by the DAC Read Ind...

Page 191: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated...

Page 192: ...must be loaded with a changed key pattern see the register description The registers will remain unlocked until the key pattern is reset by altering a significant bit In the following register descri...

Page 193: ...7 6 5 4 3 2 o REVISION LEVEL Bits 7 0 REVISION LEVEL The Trio64V is differentiated from the Trio64 by a 4 in the upper nibble of this regis ter The x in the lower nibble will change with each revision...

Page 194: ...VGA 16B Enable VGA 16 bit Memory Bus Width o 8 bit memory bus operation 1 Enable 16 bit bus VGA memory read writes This is useful in VGA text modes when VGA graphics controller functions are typi cal...

Page 195: ...ion enabled Bit 5 Reserved I 0 I R Bit 6 VGA FXPG Use Standard VGA Memory Wrapping o Memory accesses extending past a 256K boundary do not wrap 1 Memory accesses extending past a 256K boundary wrap at...

Page 196: ...LK is the external VCLK pass through feature connector clock input enabled or is divided by 2 for 4 bits pixel modes see bit 6 of AR10 or bit 4 of CR3A or is the internal DCLK if neither of the first...

Page 197: ...CI ABT PCI master aborts during DAC cycles 0 PCI master aborts handled during DAC cycles 1 PCI master aborts not handled during DAC cycles Bit 0 of this register must be cleared to 0 for this bit to b...

Page 198: ...its 5 0 of the Extended System Control 4 register CR6A this value becomes the upper 6 bits of the CPU base address and bits 3 0 of CR35 and bits 3 2 of CR51 are ignored The Tri032 only supports 2 MByt...

Page 199: ...n strapping bits are found in CR37 CR68 and CR6F 7 6 5 MEM SIZE Bits 1 0 SYS BUS System Bus Select 00 Reserved 01 VESA local bus 10 PCI local bus 11 Reserved 1 0 SYS BUS Bits 3 2 MEM MODE Memory Mode...

Page 200: ...its are found in CR36 and CR6S and CR6F 7 R 6 5 o R R R ETV Bits 0 ETV Enable Tri064V VL Bus only o Tri064V disabled except for video BIOS accesses 1 Tri064V enabled Bit 1 Reserved Bit 2 VBS Video BIO...

Page 201: ...of CR37 bits 7 0 of CR68 and bits 7 0 of 6F to be written 7 6 5 4 3 2 o 1 0 1 Miscellaneous 1 Register MISC_1 CR3A Read Write Address 3 5H Index 3AH Power On Default OOH 7 6 5 4 3 2 1 I 0 PCIRB HST EN...

Page 202: ...31 Bit 6 Reserved Bit 7 PCIRB DISA PCI Read Bursts Disabled o PCI read burst cycles enabled 1 PCI read burst cycles disabled Note Bit 7 of CR66 must be set to 1 before this bit is set to 1 Start Displ...

Page 203: ...er On Default OOH This value allows determination of the even odd row active display starting positions when operat ing in an interlaced mode This register is enabled by bit 5 of CR42 Bits 7 0 INTERLA...

Page 204: ...egister descriptions R stands for reserved write 0 read undefined See Appendix A for a table listing each of the registers in this section and its page number System Configuration Register SYS_CNFG CR...

Page 205: ...ault OOH o 6 4 I I I R I R R Bits 4 0 Reserved Bit 5 INTL MODE Interlaced Mode o Noninterlaced 1 Interlaced This bit enables the function of CR3C Bits 7 6 Reserved Extended Mode Register EXT_MODE CR43...

Page 206: ...ed Bit4 HWGC 1280 Hardware Cursor Right Storage o Function disabled 1 For 4 bits pixel the last 256 bytes in each 1 KByte line of the hardware cursor start address become the hardware graphics cursor...

Page 207: ...Three foreground color registers are stacked at this address The stack pointer com mon with CR4B is reset to 0 by reading the Hardware Graphics Cursor Mode register CR45 Each write to this register C...

Page 208: ...5 0 HWGC PAT DISP START x pas HWGC Pattern Display Start X Pixel Position This value is the offset in pixels from the left side of the 64x64 cursor pixel pattern from which the cursor is displayed Th...

Page 209: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated Bits 7 6 Reserved 18 6 SYSTEM CONTROL REGISTER DESCRIPTIONS...

Page 210: ...gisters in this section and its page number Extended System Cont 1 Register EX_SCTL_11 CR501 Read Write Address 3 5H Index 50H Power On Default OOH 7 I 6 5 I 4 3 2 1 0 GE SCR W PXL LNGH GESW 1 0 1 0 R...

Page 211: ...mory Configuration register CR31 bits 5 4 Display Start Base Address If the upper 4 display start address bits are programmed into bits 3 0 of CR69 these bits and bits 5 4 of CR31 are ignored Bits 3 2...

Page 212: ...LIN ADDR Big Endian Data Byte swap linear addressing only 00 No swap Default 01 Swap bytes within each word 10 Swap all bytes in doublewords bytes reversed 11 Reserved Bits 4 3 MMIO SELECT 00 Disable...

Page 213: ...tes reversed 11 Swap according to BE 3 0 VL Bus or C BE 3 0 PCI Byte enable settings for a bit setting of 11 b 0000 Swap all bytes in doublewords bytes reversed 0011 Swap bytes within selected word 11...

Page 214: ...of decoding used for the 64x64x2 storage array of the hard ware graphics cursor See the Programming the Hardware Cursor section for a de scription of the decoding Bits 6 5 Reserved Bit 7 TOFF VCLK Tr...

Page 215: ...ctive only when one decode wait state is selected by setting bit 4 of CR40 to 1 Bit 4 ENB LA Enable Linear Addressing o Disable linear addressing Default for VL Bus 1 Enable linear addressing Default...

Page 216: ...xx xx xx xx Bits 15 0 LlNEAR ADDRESS WINDOW POSITION LA Window Position Bits 31 16 16 bit Value the linear address window position in 32 bit CPU address space Bits 31 23 are common with bits 31 23 of...

Page 217: ...Horizontal Overflow Register EXT_H_OVF CR5D Read Write Address 3 5H Index 5DH Power On Default OOH 7 6 5 4 3 2 1 0 SFF EHS SHS EHB SHB HDE HT R 8 6 8 7 8 8 8 Bit 0 HT 8 Horizontal Total CRO Bit 8 Bit...

Page 218: ...al Blank CR15 Bit 10 Bit 3 Reserved Bit 4 VRS 10 Vertical Retrace Start CR10 Bit 10 Bit 5 Reserved Bit 6 LCM 10 Line Compare Position CR18 Bit 10 Bit 7 Reserved Extended Memory Control 3 Register EXT...

Page 219: ...efault 01 Swap bytes within each word 10 Swap all bytes in doublewords bytes reversed 11 Reserved Bit 7 Reserved Extended Miscellaneous Control Register EXT MISC CTL CR65 Read Write Address 3 5H Index...

Page 220: ...2E8H writeL15 14 to 10b Bit 2 Reserved Bit 3 PCI DIS PCI Disconnect 0 No effect 1 An attempt to write data with the Command FIFO or LPB output FIFO full or to read data with the Command FIFO not empty...

Page 221: ...Bits 3 2 STREAMS MODE 00 Streams Processor disabled 01 Secondary stream overlaid on VGA mode background 10 Reserved 11 Full Streams Processor operation primary and secondary streams from all supported...

Page 222: ...s stretching of the signal active time for CAS and OE to allow more time for valid pixel data to be available The delay time shown above is an approximation It is affected by both process and signal l...

Page 223: ...ontrol 4 Register EXT SCTL 4 CR6A ReadIWrite Address 3 5H Index 6AH Power On Default OOH 7 R 6 5 4 3 2 1 o R CPU BASE ADDRESS Bits 5 Q CPU BASE ADDRESS This field contains the upper 6 bits 19 14 of th...

Page 224: ...use by the S3 BIOS Extended BIOS Flag 4 Register EBIOS FLG4 CR6C Read Write Address 3 5H Index 6CH Power On Default OOH 7 6 5 4 3 2 o EXT BIOS FLAG REGISTER 4 Bits 7 0 EXT BIOS FLAG REGISTER 4 This r...

Page 225: ...wer up with a value of 1FH if any of PD 28 24 are not pulled low 7 R 6 5 R R Bit 0 MODE Tri064 Compatible Mode Select o The Tri064V is configured for LPB mode 1 The Tri064V is configured for Tri064 co...

Page 226: ...delay 01 2 units delay 10 1 unit delay 11 0 units delay Trio64V Integrated Graphics Video Accelerator Both the rising and falling edges of WE are delayed by the amount specified in these bits Bits 7...

Page 227: ...Trio64V Integrated Graphics Video Accelerator S3 Incorporated...

Page 228: ...ter provides information on interrupt status monitor I D and the number of bits per pixel See the Subsystem Control 42E8H Write Only register for details on enabling and clearing interrupts 15 R 14 13...

Page 229: ...9 8 7 6 5 4 GE RST FIFO ENB GE VSY 1 0 R R EMP OVF BSY ENB R R Bit 0 VSY CLR Clear Vertical Sync Interrupt Status 0 No change 1 Clear R Bit 1 GEB CLR Clear Graphics Engine Busy Interrupt Status 0 No c...

Page 230: ...14 13 12 11 10 9 8 7 6 R R R R R R R R R R Bit 0 ENB EHFC Enable Enhanced Functions 5 R 0 Enable VGA and VESA planar 4 bits pixel modes 4 LA 1 Enable all other modes Enhanced and VESA non planar Bit...

Page 231: ...gister produces the current vertical drawing coordinate Bits 11 0 CURRENT V POSITION Bits 15 12 Reserved Current X Position Register CUR_X Read Write Address 86E8H Power On Default Undefined For line...

Page 232: ...line from point A to point B determine the change in the X coordinate from A to B and the change in the V coordinate from A to B Take the smaller of the two changes and multiply its absolute value by...

Page 233: ...1 if the starting X the ending X Error Term 2 min ldxl ldyi max ldxl ldYI if the starting X the ending X See the Destination Y Position Axial Step Constant 8AE8H register for an explanation of the ter...

Page 234: ...its 15 11 pro vide the upper 5 FIFO status bits 0000000000000 13 FIFO slots available 0000000000001 12 FIFO slots available 0000000000011 11 FIFO slots available 0000000000111 10 FIFO slots available...

Page 235: ...raw will not be drawn Bit 3 DIR TYP Select Radial Direction Type o x y axial 1 Radial Bit 4 DRAW YES Draw Pixel 0 Move the current position only don t draw 1 Draw pixel s Bits 7 5 DRWG DIR Select Draw...

Page 236: ...high byte second Bits 15 13 CMD TYPE Select Command Type 000 NOP This is used to set up short stroke vector drawing without writing a pixel 001 Draw Line If bit 3 of this register is cleared to 0 the...

Page 237: ...I 13 12 11 I 10 I 9 I 8 7 I 6 I 5 2 DRWG DIR DRW PIXEL LENGTH DRWG DIR 1 0 MV 3 Bits 3 0 PIXEL LENGTH Value pixels 1 2 Bit 4 DRW MV Draw Pixel 1 0 2 o Move current position only don t draw 1 Draw pix...

Page 238: ...e accessed If RSF 1 the upper 16 bits are accessed The RSF flag toggles automatically when a doubleword is read or written Foreground Color Register FRGD_COLORI Read Write Address A6E8H Power On Defau...

Page 239: ...F flag toggles automatically when a double word is read or written Bitplane Read Mask Register RD_MASK Read Write Address AEE8H Power On Default Undefined 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I...

Page 240: ...lewords are read or written sequen tially depending on the state of the RSF flag bit 4 of BEE8H Index EH If RSF 0 the lower 16 bits are accessed If RSF 1 the upper 16 bits are accessed The RSF flag to...

Page 241: ...ad of this register produces a read of the register specified by bits 2 0 of the Read Register Select BEE8H Index OFH register Each read of BEE8H causes the read index bits 2 0 of BEE8H Index OFH to i...

Page 242: ...15 12 INDEX OH Top Scissors SCISSORS_T Write Only Address BEE8H Index 1H Power On Default Undefined This register specifies the top of the clipping rectangle It is the lowest Y value that will be dra...

Page 243: ...This register specifies the right side of the clipping rectangle It is the highest X value that will be drawn Bits 11 0 CLIPPING RIGHT LIMIT Bits 15 12 INDEX 4H Pixel Control Register PIX_CNTL Write O...

Page 244: ...is in the 2nd MByte of display memory 010 First destination memory address is in the 3rd MByte of display memory 011 First destination memory address is in the 4th MByte of display memory This field s...

Page 245: ...display memory 10 First source memory address is in the 3rd MByte of display memory 11 First source memory address is in the 4th MByte of display memory This field is superseded by bits 6 4 of BEE8H I...

Page 246: ...OEH Read Register Select Register READ_SELl Write Only Address BEE8H Index OFH Power On Default Undefined Bits 3 0 READ REG SEL Read Register Select When BEE8H is read the value returned is determine...

Page 247: ...ined All data from the CPU to the Graphics Engine must pass through this register Bits 15 0 IMAGE WRITE DATA Pixel Data Transfer Extension Register PIX_TRANS_EXT Write Only Address E2EAH Power On Defa...

Page 248: ...7 R R R R R R R R R 31 30 29 28 27 26 25 24 23 R PSFC R PSIDF R Bits 23 0 Reserved Bits 26 24 PSIDF Primary Stream Input Data Format 000 RGB 8 CLUT 001 Reserved 010 Reserved 011 KRGB 16 1 5 5 5 100 R...

Page 249: ...26 24 RGB CC RGB Color Comparison Precision 000 Compare bit 7 of RGB compare red bit 7 s green bit 7 s and blue bit 7 s 001 Compare bits 7 6 of RGB 010 Compare bits 7 5 of RGB 011 Compare bits 7 4 of...

Page 250: ...alue does not take effect until the next VSYNC Bits 23 12 Reserved Bits 26 24 SDIF Secondary Stream Input Data Format 000 Reserved 001 YCbCr 16 4 2 2 16 240 input range 010 YUV 16 4 2 2 0 255 input ra...

Page 251: ...14 13 12 11 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I R R R R R K2 HORIZONTAL SCALE FACTOR 31 30 29 28 27 26 I 25 I 24 I 23 I 22 I 21 I 20 I 19 I 18 I 17 I R R R R R K1 HORIZONTAL SCALE FACTOR Bits 10...

Page 252: ...e primary stream blend coefficient When this field is programmed the value does not take effect until the next VSYNC Bits 23 13 Reserved Bits 26 24 Compose Mode 000 Secondary stream opaque overlay on...

Page 253: ...stream frame buffer starting address 0 This value must be quadword aligned Bits 31 22 Reserved Primary Stream Frame Buffer Address 1 MM81C4 Read Write Address 81C4H Power on Default Undefined If the p...

Page 254: ...in the primary stream buffer s If double buffering is used the stride must be the same for both buffers Bits 31 12 Reserved Double Buffer LPB Support MM81CC Read Write Address 81CCH Power on Default...

Page 255: ...used for the LPB input stream Which alternative applies is determined by the LPB starting address register selected by bit 4 of this register Bit 3 Reserved Bit 4 LIS LPB Input Buffer Select 0 LPB fr...

Page 256: ...ream frame buffer starting address 0 This value must be quadword aligned Bits 31 22 Reserved Secondary Stream Frame Buffer Address 1 MM81 04 Read Write Address 81 D4H Power on Default Undefined If the...

Page 257: ...on Default Undefined except bits 31 30 are OOb When an opaque overlay mode is being used bits 26 24 of MM81AO OOOb or 001b the fields in this register can be programmed to eliminate the fetching of t...

Page 258: ...of this register If the secondary stream is the background the value is XO X1 x bytes per pixel 8 1 Bits 18 13 Reserved Bits 28 19 Pixel Resume Fetch Value Offset in quadwords from the background sta...

Page 259: ...the value does not take effect until the next VSYNC Bits 31 11 Reserved K2 Vertical Scale Factor MM81E4 ReadIWrite Address 81E4H Power on Default OOOOOOOOH 15 14 13 12 11 10 1 9 I 8 j 7 I 6 I 5 I 4 I...

Page 260: ...8 I 7 I 6 I 5 4 I 3 121 1 I 0 PFIFO THRESHOLD SFIFO THRESHOLD FIFO ALLOCATION 30 I 29 I 28 I 27 I 26 25 I 24 I 23 I 22 I 21 20 I 19 I 18 I 17 I 16 R I R I R I R I R R I R I R I R I R R I R IEWS I R I...

Page 261: ...y o Standard 2 cycle memory operation 1 1 cycle EDO memory operation requires EDO memory capable of this This bit is only valid for 64 bit PD bus operation 2 or 4 MBytes of memory It should not be set...

Page 262: ...umber of pixels 1 displayed in each line in the primary stream window Bits 31 27 Reserved Secondary Window Start Coordinates MM81F8 Read Write Address 81 F8H Power on Default Undefined 15 14 13 12 11...

Page 263: ...NDARY STREAM HEIGHT 31 30 29 28 27 26 I 25 I 24 I 23 I 22 I 21 I 20 I 19 I 18 I 17 I 16 R R R R R SECONDARY STREAM WIDTH Bits 10 0 Secondary Stream Height Value Number of lines displayed in the second...

Page 264: ...epends on which LPB mode is enabled via bits 3 1 of this register or which feature connector option is selected Once enabled the LPB is reset either by a system reset or via bit 4 of this register Bit...

Page 265: ...g a 1 to this bit causes the Trio64V to do whatever functions it is programmed to do upon receipt of a VSYNC For example values programmed in certain registers only take effect at the next VSYNC Bit 1...

Page 266: ...ows for the LPB to be used in pass through mode MMFFOO_3 1 100b when the Tri064V is configured for compatible mode The LPB is normally driven by LCLK but this is not available in compatible mode Bit 2...

Page 267: ...Output FIFO Full o Output FIFO not full 1 Output FIFO full 9 R 25 R Bit 12 OFE LPB Output FIFO Empty o Output FIFO not empty 1 Output FIFO empty 8 R 24 R Bit 13 OFAE LPB Output FIFO Almost Empty 7 6...

Page 268: ...us o No interrupt 1 LPB output FIFO empty Writing a 1 to this bit clears the interrupt Bit 1 ELI End of Line Interrupt Status o No interrupt R 5 R 21 R 4 R 20 R 1 The Tri064V has received an HSYNC inp...

Page 269: ...of Frame Interrupt Enable Mask o End of frame interrupt disabled 1 End of frame interrupt enabled Bit 19 SPM Serial Port Start Detect Interrupt Mask o Serial port start detect interrupt disabled 1 Ser...

Page 270: ...ress o The value must start on an 8 byte boundary Bits 31 22 Reserved LPB Frame Buffer Address 1 MMFF10 Read Write Address FF10H Power on Default Undefined 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6...

Page 271: ...21 n Transaction Type Scenic MX2 000 Register write 001 Register read 110 Compressed video data write from the output FIFO This value is automatically generated by hardware when data is written to the...

Page 272: ...Data Port Read only Whenever a write is performed to CR5C STWR is asserted low This strobe can be used to enable a register to drive data onto any or all of the LD 7 4 lines This data is then latched...

Page 273: ...SDR Serial Data Read Read Only o Pin 206 is low 1 Pin 206 is tri stated no device is driving this line Bit 4 SPE Serial Port Enable 0 Use of bits 1 0 of this register disabled 1 Use of bits 1 0 of th...

Page 274: ...9 28 27 I 26 I 25 I 24 I 23 I 22 I 21 I 201 19 1 18 I 17 1 R R R R I R I R I VIDEO INPUT WINDOW HEIGHT Bits 11 0 Video Input Line Width Value pixels x 2 2 for Video 8 mode Value pixels 2 for Video 16...

Page 275: ...a line Bits 31 25 Reserved LPB Horizontal Decimation Control MMFF2C Read Write Address FF2CH Power on Default Undefined 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 VIDEO DATA B...

Page 276: ...sed to the video memory If a vertical video data offset is specified in MMFF28_24 16 video 8 or 16 modes only decimation does not align with the starting line after the offset and instead starts from...

Page 277: ...icient use of the MOVSD assembly language instruction Accesses must be to doubleword addresses 15 I 14 I 13 I 12 I 11 I 10 L 9 J 8 I 7 I 6 I 5 j 4 I 3 I 2 1 1 I 0 OUTPUT FIFO DATA 31 I 30 I 29 I 28 I...

Page 278: ...n read or write command is issued the AD 7 0 lines contain the address of the register in this space to be accessed The Tri064V supports or returns 0 for the first 64 bytes of this space In the follow...

Page 279: ...io64V can generate and respond to 15 R 14 13 12 11 10 9 8 7 6 R R R R R R R R R Bit 0 I O Enable Response to I O Accesses o Response to I O space accesses is disabled 1 Response to I O space accesses...

Page 280: ...Read Only Address 08H Power On Default 30000H This register is hardwired to 300004xH The 3 specifies that the Tri064V is a VGA compatible display controller The x in the revision ID will change with e...

Page 281: ...address bits 31 26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 j 1 0 R R R R R R R R R R R R PREF MSI 0 TYPE 00 0 Bit 0 MSI Memory Space Indicator value 0 base registers map into memory space hardwired Bits 2 1...

Page 282: ...BIOS ROM address space defined in this register are disabled 1 Accesses to the BIOS ROM address space defined in this register are enabled Bits 15 1 Reserved Bits 31 16 BIOS ROM BASE ADDRESS These are...

Page 283: ...ator S3 Incorporated Interrupt Pin Read Only Address 3DH Power On Default 01H This register specifies that INTA is the interrupt pin used 7 6 5 4 3 2 1 o INTERRUPT PIN Bits 7 0 INTERRUPT PIN value 01H...

Page 284: ...ta book VGA S3VGA System Control System Extension Enhanced Commands Streams Processor LPB PCI Configuration Space Within each table registers are listed in order of increasing addresses indices Name a...

Page 285: ...tive low signal 3CC Miscellaneous Output 16 1 0 R Color emulation Address based at 3Dx 1 R Enable CPU access of video memory 3 2 R Video DCLK select Enable DCLK PLL loading 4 R Reserved 5 R Select the...

Page 286: ...00 Reset SRO 16 6 0 RNV Asynchronous reset not functional for the Tri064V 1 RNV Synchronous reset not functional for the Tri064V 7 2 RNV Reserved 3C5 01 Clocking Mode SR1 16 6 0 RNV Character clocks...

Page 287: ...Use VCLKI for internal dot clock functions test only 1 R W Pixel data from VAFC latched by VCLKI 2 R W Reserved 3 R W Enable 24 bits pixel 7 4 R W Specify color mode for feature connector input 3C5 00...

Page 288: ...in 147 test only 3 RNV VCLK direction determined by EVCLK 4 RNV Divide DCLK by 2 5 RNV Load MCLK and DCLK PLL values immediately 6 RNV Invert DCLK 7 RNV Enable 2 MCLK memory writes 3C5 16 CLKSVN Test...

Page 289: ...4 0 RM End position of horizontal blanking 6 5 RM Display enable skew in character clocks 7 RM Reserved 375 04 Start Horizontal Sync Position CR4 16 24 7 0 RM Character count where HSYNC qoes active...

Page 290: ...dress 375 00 Start Address Low CRD 16 28 7 0 RNV Bits 7 0 of the display start address 375 OE Cursor Location Address High Hardware Cursor 16 28 Foreground Color in Enhanced Mode CRE 7 0 RNV Bits 15 8...

Page 291: ...count by 2 mode 4 RNI Reserved 5 RNI Enable CGA mode address wrap 6 RNI Use byte address mode 7 RNI Horizontal and vertical retrace signals enabled 375 18 Line Compare CR18 16 34 7 0 RNI Line at which...

Page 292: ...4 R VV Select odd even addressing 5 R VV Select odd even shift mode 6 R VV Select 256 color shift mode 7 R VV Reserved 3CF 06 Memory Map Mode Control GR6 16 41 0 R VV Select graphics mode memory addre...

Page 293: ...plane enable 5 4 RNV Select inputs to bits 5 4 of 3 AH 7 6 RNV Reserved 3C1 0 13 Horizontal Pixel Panning AR13 16 47 3 0 RNV Number of pixels to shift the display to the left 7 4 RNV Reserved 3C1 0 14...

Page 294: ...17 2 7 0 R 4x 375 30 Chip ID Rev CR30 17 2 3 0 R Chip Identification EH 7 4 R Chip revision status stepping See CR2F 375 31 Memory Configuration CR31 17 3 0 RNV Enable base address offset CR6A 6 0 1...

Page 295: ...page mode fast page EDO or 1 cycle EDO 4 RNJ Enable BIOS ROM accesses VL Bus 7 5 RNJ Define display memory size 375 37 Configuration 2 CR37 17 8 0 RNJ Enable Trio32 64 operation VL Bus 1 RNJ Reserved...

Page 296: ...egisters are read write protected at power up by hardware reset In order to read write these registers the Register Lock 2 register CR39 must be loaded with a binary unlock key pattern see the registe...

Page 297: ...11 RNI Reserved 375 48 49 Hardware Graphics Cursor Origin V CR48 CR49 18 4 10 0 RNI V coordinate of the hardware cursor upper line 15 11 RNI Reserved 375 4A Hardware Graphics Cursor Foreground Stack...

Page 298: ...address bits 19 18 3 2 R W Old CPU base address bits 19 18 5 4 R W Logical screen width bits 9 8 7 6 R W Reserved 375 52 Extended BIOS Flag 1 CR52 19 3 7 0 R W Used by the video BIOS 375 53 Extended M...

Page 299: ...I Linear addressing window position bits 31 16 375 5C General Out Port CR5C 19 8 7 0 RNI General Output Port 375 5D Extended Horizontal Overflow CR5D 19 8 0 RNI Horizontal total bit 8 CRO 1 RNI Horizo...

Page 300: ...NI Software reset of the Graphics Engine 2 RNI Reserved 3 RNI PCI disconnect on write with FIFO full or read with FIFO empty 5 4 RNI Reserved 6 RNI PAl15 0J are tri stated off 7 RNI Enable PCI bus dis...

Page 301: ...video BIOS 375 6C Extended BIOS Flag 4 CR6C 19 15 7 0 RMJ Used by the video BIOS 375 60 Extended BIOS Flag 5 CR6D 19 15 7 0 RMJ Used by the video BIOS 375 6E Extended BIOS Flag 6 CR6E 19 16 7 0 RMJ U...

Page 302: ...em Control 20 2 0 W Clear vertical sync interrupt status 1 W Clear Graphics Engine busy interrupt status 2 W Clear Command FIFO overflow interrupt status 3 W Clear Command FIFO empty interrupt status...

Page 303: ...d Bits 15 14 for step constant 92E8 Line Error Term 20 6 13 0 RNJ Error term for line draws 15 14 RNJ Reserved 96E8 Major Axis Pixel Count 20 6 11 0 RNJ Lenqth of the lonqest axis pixels 1 15 12 RNJ R...

Page 304: ...ina bit olane AEES BitDlane Read Mask 20 12 31 0 R W Each bit enables readinq of correspondinq bit plane B2ES Color Compare 20 13 31 0 R W Color value to be comoared with current bitmap color B6ES Bac...

Page 305: ...dress location in memory 11 7 W Reserved 15 12 W ODH index BEES E Multifunction Control Miscellaneous 20 1S 1 0 W Destination base address bits 21 20 3 2 W Source base address bits 21 20 4 W Select up...

Page 306: ...lower bound for chroma 26 24 RNJ RGB color com arisOnfJrecision 27 RNJ Reserved 28 RNJ Color key control full compare or bit 16 of 1 5 5 5 31 29 RNJ Reserved 8190 Secondary Stream Control 21 3 11 0 R...

Page 307: ...startinq address 1 31 22 RMJ Reserved 81C8 Primary Stream Stride 21 7 11 0 RMJ Primary stream stride 31 12 RMJ Reserved 81CC Double Buffer LPB Support 21 7 0 RMJ Select primary frame buffer address 1...

Page 308: ...factor 31 11 RNJ Reserved 81E8 DDA Vertical Accumulator Initial Value 21 13 11 0 RNJ DDA vertical accumulator initial value 31 12 RNJ Reserved 81EC Streams FIFO and RAS Controls 21 13 4 0 RNJ Streams...

Page 309: ...Bit s R W Bit Description Page 81F8 Secondary Stream Window Start Coordinates 21 15 10 0 RM Secondary stream Y start 15 11 RM Reserved 26 16 RM Secondary stream X start 31 27 RM Reserved 81FC Seconda...

Page 310: ...rrently pointed to 15 14 RNV Reserved 17 16 RNV Maximum compressed data bust size 20 18 RNV Reserved 22 21 RNV Video FIFO threshold 23 RNV Reserved 24 RNV LPB clock driven by LCLK 25 RNV Don t add str...

Page 311: ...serial port start condition detect interrupt 23 20 RNJ Reserved 24 RNJ Drive SPCLK Iowan receipt of a serial port start condition 31 25 RNJ Reserved FFOC LPB Frame Buffer Address 0 22 7 21 0 RNJ LPB f...

Page 312: ...at E2H 10 R Bit 2 mirror data on byte lane 2 at E2H 11 R Bit 3 mirror data on byte lane 2 at E2H 12 R Bit 4 mirror data on byte lane 2 at E2H 31 13 RMJ Reserved FF24 LPB Video Input Window Size 22 11...

Page 313: ...snooping 15 6 RNI Reserved 06 Status 23 3 8 0 RNI Reserved 10 9 RNI Hardwired to select medium device select timing 15 11 RNI Reserved 08 Class Code 23 3 31 0 R Hardwired to indicate VGA compatible di...

Page 314: ...1 4 enable 21 2 clipping 15 8 20 15 20 16 20 18 clock generator DC specifications 4 1 frequency synthesis 9 1 new DCLK PLL load 16 17 new MCLK and DCLK PLL load 16 18 new MCLK PLL load 16 17 color com...

Page 315: ...axial step constant 20 5 background color 20 11 background foreground mix 20 13 clipping 20 15 20 16 20 18 color compare 20 13 20 18 color depth 19 1 command types 20 9 current X position 20 4 current...

Page 316: ...terlaced operation 17 12 18 2 interrupt enable 12 11 17 4 FIFO empty interrupt enable 20 3 FIFO empty interrupt status 20 1 FIFO overflow interrupt enable 20 2 FIFO overflow interrupt status 20 1 gene...

Page 317: ...20 1 4 INDEX PCIBus BIOS ROM access enable 23 5 BIOS ROM base address 23 5 configuration 6 1 configuration space 6 1 cycles 6 1 device I D 6 1 DEVSEL timing 6 1 disable read bursts 17 11 disconnection...

Page 318: ...s select 19 16 register 22 9 22 10 short stroke vector 15 22 20 10 solid line drawing 15 9 source base address 20 17 SRDY delay assertion 18 1 generation 6 6 start address 16 28 start horizontal blank...

Page 319: ...ync active status 16 3 control for power management 16 13 polarity 16 2 vertical total 16 25 VGAcompatibility 14 1 16 1 VGA graphics mode select 16 45 VGA memory bus width 17 3 VGA memory mapping 17 3...

Page 320: ...53 Incorporated 2770 San Tomas Expwy Santa Clara CA 95051 0968 Tel 408 980 5400 Fax 408 980 5444 Printed in U S A on recycled paper DB018 A...

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