DO100
DPLL
BRIGHTNESS
bl1-5
USB
MODE
DPLL 1~9, the lower the value, the smaller the clock jitter
.
This DPLL setting is a unique function of ESS series products. It can adjust the bandwidth
of the DPLL digital phase-locked loop circuit inside the chip, so that the chip can
achieve a balance between anti-clock jitter and input tolerance.
Effect:
When the clock stability of the input signal is good, this value can be reduced,
so that the clock performance of the system is better;
When the clock stability of the input signal is not good, the sound may be
interrupted. Increasing this value can avoid the occurrence of audio
interruption! Especially when using TV as the signal source.
UAC1
(
USB1.1 description: when USB1.1 is selected, the WIN system is free of drive,
and supports sampling rate 44.1-96kHz, 24bit
)
UAC2
(select USB2.0, WIN system needs to install driver, support DSD)
Summary of Contents for DO100
Page 1: ...Ver 1 0 USER MANUAL Do100...
Page 2: ...7 1 2 3 4 QC 5 6 DO100...
Page 5: ...2 7 AAA DO100 FN...
Page 7: ...DO100 INPUT USB USB BT OPT COA 0 5 1 2 5 bl...
Page 8: ...DO100 FL1 FL2 FL3 Apodizing FL4 FL5 FL6 FL7 Brickwall PCM FILTER PCM...
Page 9: ...DO100 DPLL DPLL 1 9 BRIGHTNESS bl1 5 1 5 DPLL ESS DPLL USB USB U1 1 USB1 0 U2 0 USB2 0 WIN...
Page 18: ...DO100 1 2 3 4 QC 5 6 S M S L 7 1...
Page 21: ...DO100 No 7 AAA 2 FN...
Page 23: ...DO100 INPUT USB USB BT OPT COA 0 5 1 5 bl...
Page 24: ...DO100 FL1 FL2 FL3 FL4 FL5 FL6 FL7 PCM FILTER PCM...
Page 25: ...DO100 DPLL DPLL 1 9 BRIGHTNESS BL1 5 DPLL ESS DPLL USB USB U1 1 USB1 0 U2 0 USB2 0 WIN...