RTD Embedded Technologies, Inc.
|
www.rtd.com
12
FPGA35S6046/FPGA35S6101 User’s Manual
3.3
Connectors and Jumpers
Figure 2: Board Connections
3.3.1
E
XTERNAL
I/O
C
ONNECTORS
CN3: Xilinx JTAG Programming Header
Connector CN3 provides a connection to the Xilinx JTAG programming header. The pin assignment for CN3 is shown below. This connector
header mates with the Xilinx OEM programming cable.
Table 4: CN3 Programming Header
3.3V VRef
2
1
GND
TMS
4
3
GND
TCK
6
5
GND
TDO
8
7
GND
TDI
10
9
GND
N/C
12
11
GND
N/C
14
13
GND
JP4, JP5 & JP6:
Pull up/Pull down
Jumper
B2 on bottom side
CN11: RS-232/422/485
CN12: RS-232/422/485
CN13: RS-232/422/485
JP1: Embedded
Programmer
Enable
JP8: User ID
Jumper
CN3:
Programming
Header
CN1 & CN2: PCIe Connector
CN8: High Speed Digital I/O
CN10: RS-232/422/485
CN9: Digital I/O
