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DM35425HR User’s Manual

6.4

BAR2

–

DAC Functional Block

This Function Block is for a Digital to Analog converter. This DAC Function block has multiple channels. There are 4 channels in this functional
block, however all channels must use the same pacer clock. Each channel has its own FIFO and DMA channel.

Table 19: Multi-Channel DAC Functional Block

Offset

0x03

0x02

0x01

0x00

H

ea

de

r

FB + 0x00

FB_ID

FB + 0x04

FB_DMA_BUFFERS

FB_DMA_CHANNELS

Reserved

Reserved

D

AC

C

ont

rol

FB + 0x08

STOP_TRIG

START_TRIG

CLK_SRC

MODE_STATUS

FB + 0x0C

CLK_DIV

FB + 0x10

CLK_DIV_CNTR

FB + 0x14

Reserved

FB + 0x18

POST_STOP_CONVERSIONS

FB + 0x1C

CONVERSION_CNT

FB + 0x20

INT_ENA (Conversion, Start, Stop, Error, Channel)

FB + 0x24

INT_STAT

Reserved

FB + 0x28

CLK_BUS3

CLK_BUS2

BOOKMARK_TRIG

FB + 0x2C

CLK_BUS7

CLK_BUS6

CLK_BUS5

CLK_BUS4

FB + 0x30

Reserved

D

AC

C

ha

nn

el

0

FB + 0x34

CH0_FRONT_END_CONFIG (Maskable register

–

16-bit)

FB + 0x38

CH0_FIFO_DATA_CNT

FB + 0x3C

CH0_MARK_INT_ENA

CH0_MARK_INT_STAT

Reserved

Reserved

FB + 0x40

Reserved

FB + 0x44

CH0_LAST_CONVERSION

D

AC

C

ha

nn

el 1

FB + 0x48

CH1_FRONT_END_CONFIG (Maskable register

–

16-bit)

FB + 0x4C

CH1_FIFO_DATA_CNT

FB + 0x50

CH1_ MARK_INT_ENA

CH1_ MARK_INT_STAT

Reserved

Reserved

FB + 0x54

Reserved

FB + 0x58

CH1_LAST_ CONVERSION

D

AC

C

ha

nn

el 2

FB + 0x5C

CH2_FRONT_END_CONFIG (Maskable register

–

16-bit)

FB + 0x60

CH2_FIFO_DATA_CNT

FB + 0x64

CH2_ MARK_INT_ENA

CH2_ MARK_INT_STAT

Reserved

Reserved

FB + 0x68

Reserved

FB + 0x6C

CH2_LAST_ CONVERSION

D

AC

C

ha

nn

el 3

FB + 0x70

CH3_FRONT_END_CONFIG (Maskable register

–

16-bit)

FB + 0x74

CH3_FIFO_DATA_CNT

FB + 0x78

CH3_ MARK_INT_ENA

CH3_ MARK_INT_STAT

Reserved

Reserved

FB + 0x7C

Reserved

FB + 0x80

CH3_LAST_ CONVERSION

D

AC

FIF

O

FB + 0x84

CH_FIFO_ACCESS (DAC Channel 0)

FB + 0x88

CH_FIFO_ACCESS (DAC Channel 1)

FB + 0x8C

CH_FIFO_ACCESS (DAC Channel 2)

FB + 0x90

CH_FIFO_ACCESS (DAC Channel 3)

6.4.1

FB_ID

(R

EAD

-O

NLY

)

This is the functional block ID. This register should read 0x01032000 for the D\A functional block.

6.4.2

FB_DMA_CHANNELS

(R

EAD

-O

NLY

)

This register contains the number of DMA Channels in this Function Block. Each Channel contains a control register, and a set of Buffer
Descriptor Registers.

6.4.3

FB_DMA_BUFFERS

(R

EAD

-O

NLY

)

This register contains the number of Buffer Descriptors in each DMA Channel.

6.4.4

M

ODE

_S

TATUS

(R

EAD

/W

RITE

,

R

EAD

-O

NLY

)

Selects the current mode of operation and indicates its triggering status.

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Summary of Contents for DM35425

Page 1: ...DM35425HR PCI Express Data Acquisition Board User s Manual BDM 610010047 Rev E ...

Page 2: ... persons qualified to service electronic equipment Contents and specifications within this manual are given without warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2017 by RTD Embedded Technologies Inc All rights reserved RT...

Page 3: ...l I O Connector 15 Other Connectors 16 3 3 3 Jumpers 16 3 4 Steps for Installing 17 4 IDAN Connections 18 4 1 Module Handling Precautions 18 4 2 Physical Characteristics 18 4 3 Connectors 18 4 3 1 Bus Connectors 18 CN1 Top CN2 Bottom PCIe Connector 18 4 4 Connectors 19 4 4 1 External I O Connectors 19 P2 Connector 68 pin Subminiature D Female Connector 19 P3 Connector 68 pin Subminiature D Female ...

Page 4: ...te 34 6 2 4 FB_DMAm_Stat_Used Read Write 34 6 2 5 FB_DMAm_Stat_Invalid Read Write 34 6 2 6 FB_DMAm_Stat_Overflow Read Write 34 6 2 7 FB_DMAm_Stat_Underflow Read Write 34 6 2 8 FB_DMAm_Stat_Complete Read Write 34 6 2 9 FB_DMAm_Current_Buffer Read Only 34 6 2 10 FB_DMAm_COUNT Read Only 34 6 2 11 FB_DMAm_RD_FIFO_CNT Read Only 34 6 2 12 FB_DMAm_WR_FIFO_CNT Read Only 35 6 2 13 FB_DMAm_ADDRESSn Read Wri...

Page 5: ... 5 BAR2 Advanced Digital I O Functional Block 46 6 5 1 FB_ID Read Only 46 6 5 2 FB_DMA_CHANNELS Read Only 46 6 5 3 FB_DMA_BUFFERS Read Only 46 6 5 4 Mode_Status Read Write Read Only 46 6 5 5 CLK_SRC Read Write 47 6 5 6 START_TRIG Read Write 47 6 5 7 STOP_TRIG Read Write 47 6 5 8 CLK_DIV Read Write 47 6 5 9 CLK_DIV_CNTR Read Only 47 6 5 10 PRE_TRIGGER_CAPTURE Read Write 48 6 5 11 POST_STOP_CAPTURE ...

Page 6: ...igure 8 DM35425 Block Diagram 24 Figure 9 Filter Response with each ORDER Value 40 Figure 10 DM35425HR Trimpots 53 Table of Tables Table 1 Ordering Options 8 Table 2 Operating Conditions 10 Table 3 Electrical Characteristics 10 Table 4 CN3 Differential Mode Pin out 15 Table 5 CN3 Single Ended Mode Pin out 15 Table 6 CN4 Differential Mode Pin out 16 Table 7 CN4 Single Ended Mode Pin out 16 Table 8 ...

Page 7: ...nal Block 51 Table 23 Data Values for Calibrating Bipolar 10 V Range 54 Table 24 Data Values for Calibrating Bipolar 20 V Range 54 Table 25 ADC Bit Weights Bipolar 54 Table 26 Data Values for Calibrating Bipolar 20 V Range 55 Table 27 ADC Bit Weights Unipolar 55 Table 28 Trimpots for Calibrating ADC Gain 55 Table 29 DAC Bit Weights 56 Table 30 Trimpots for Calibrating DAC Gain 56 ...

Page 8: ...0 10V output ranges o 7 µs full scale settling time Advanced Digital I O o 32 bit port of digital I O o Bit programmable direction o Advanced digital interrupts o Parallel Bus Mode External Clocking o Provides 6 external clocking pins that can be used as inputs or outputs o Provides external triggering o External gate for each clock pin 1 3 Ordering Information The DM35425 is available with the fo...

Page 9: ...AL SUPPORT If you are having problems with you system please try the steps in the Troubleshooting section of this manual on page 57 For help with this product or any other product made by RTD you can contact RTD Embedded Technologies technical support via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail techsupport rtd com ...

Page 10: ...erential TX Impedance 80 120 Ω Differential Input Voltage 0 175 1 2 V DC Differential RX Impedance 80 120 Ω Electrical Idle Detect Threshold 65 175 mV Analog to Digital Converter Linear Input Voltage IN or IN 10 10 V FSR Full Scale Differential Input Voltage VIN IN IN G PGA Gain 5 𝐺 4 99878 𝐺 V Resolution 12 Bits Data Rate 1 25 MSPS Input Impedance 6 MΩ ENOB Inputs 0 8dBFS 10Khz Single Ended 5V 11...

Page 11: ...cal Max Unit Resolution 12 Bits Relative Accuracy 1 LSB Gain Error 2 LSB Settling Time 5 µs Output Current 5 mA Slew Rate 2 V µs G Gains 1 2 Output Impedance 45 Ω Digital I O VIL Input High Voltage 2 5 5 V VIH Input Low Voltage 0 5 0 8 V VOL Output Low Voltage IO 12mA 0 0 0 4 V VOH Output High Voltage IO 12mA 2 6 3 3 V 5V Output CN3 CN4 200 mA ...

Page 12: ...FT absolute value was calculated using 8192 data sample Figure 1 Channel FFT 2 2 2 ANALOG INPUT HISTOGRAMS In Figure 2 you can see a histogram of samples from sampling a grounded input in 10 V differential input range The number of samples is 32768 Figure 2 Histogram 140 120 100 80 60 40 20 0 0 100 200 300 400 500 600 dB FS Frequency kHz 0 5000 10000 15000 20000 25000 30000 1 0 1 Frequency Bin ADC...

Page 13: ...l you are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware 3 2 Physical Characteristics Weight Approximately 55 g 0 12 lbs Dimensions 90 17 mm L x 95 89 mm W 3 550 in L x 3 775 in W Figure 3 ...

Page 14: ...om PCIe Connector The PCIe connector is the connection to the system CPU The position and pin assignments are compliant with the PCI 104 Express Specification See PC 104 Specifications on page 58 The DM35425 is a Universal board and can connect to either a Type 1 or Type 2 PCIe 104 connector CN1 CN2 PCIe Connector CN3 Analog Digital I O CN4 Analog Digital I O ...

Page 15: ...D 21 22 AGND DIO7 23 24 DIO15 DIO6 25 26 DIO14 DIO5 27 28 DIO13 DIO4 29 30 DIO12 DIO3 31 32 DIO11 DIO2 33 34 DIO10 DIO1 35 36 DIO9 DIO0 37 38 DIO8 EXT_CLK_2 39 40 GND EXT_CLK_3 41 42 EXT_CLK_4 EXT_CLK_5 43 44 EXT_CLK_6 EXT_CLK_7 45 46 Reserved Reserved 47 48 5V Reserved 49 50 GND Table 5 CN3 Single Ended Mode Pin out AIN0 1 2 AIN8 AIN1 3 4 AIN9 AIN2 5 6 AIN10 AIN3 7 8 AIN11 AIN4 9 10 AIN12 AIN5 11...

Page 16: ...44 EXT_CLK_GATE6 EXT_CLK_GATE7 45 46 Reserved Reserved 47 48 5V Reserved 49 50 GND Table 7 CN4 Single Ended Mode Pin out AIN16 1 2 AIN24 AIN17 3 4 AIN25 AIN18 5 6 AIN26 AIN19 7 8 AIN27 AIN20 9 10 AIN28 AIN21 11 12 AIN29 AIN22 13 14 AIN30 AIN23 15 16 AIN31 AOUT2 17 18 AGND AOUT3 19 20 AGND AGND 21 22 AGND DIO23 23 24 DIO31 DIO22 25 26 DIO30 DIO21 27 28 DIO29 DIO20 29 30 DIO28 DIO19 31 32 DIO27 DIO1...

Page 17: ...operly positioned 6 Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule 7 Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack 8 Gently and evenly press the module onto the PC 104 stack 9 If any boards are to be stacked above this module install them 10 Attach any necessary...

Page 18: ...tic environment and use a grounded workbench for testing and handling of your hardware 4 2 Physical Characteristics Weight Approximately 0 33 Kg 0 72 lbs Dimensions 151 972 mm L x 129 978 mm W x 34 011 mm H 5 983 in L x 5 117 in W x 1 339 in H Figure 6 IDAN Dimensions 4 3 Connectors 4 3 1 BUS CONNECTORS CN1 Top CN2 Bottom PCIe Connector The PCIe connector is the connection to the system CPU The po...

Page 19: ... AIN7 CN3 15 16 AIN7 AIN15 CN3 16 17 AOUT0 CN3 17 18 AGND CN3 18 19 AOUT1 CN3 19 20 AGND CN3 20 21 AGND CN3 21 22 AGND CN3 22 23 DIO7 CN3 23 24 DIO15 CN3 24 25 DIO6 CN3 25 26 DIO14 CN3 26 27 DIO5 CN3 27 28 DIO13 CN3 28 29 DIO4 CN3 29 30 DIO12 CN3 30 31 DIO3 CN3 31 32 DIO11 CN3 32 33 DIO2 CN3 33 34 DIO10 CN3 34 Table 8 IDAN DM35425 68 Pin Subminiature D Connector IDAN Pin Signal DM35425 Pin 35 DIO1...

Page 20: ...N4 16 17 AOUT2 CN4 17 18 AGND CN4 18 19 AOUT3 CN4 19 20 AGND CN4 20 21 AGND CN4 21 22 AGND CN4 22 23 DIO23 CN4 23 24 DIO31 CN4 24 25 DIO22 CN4 25 26 DIO30 CN4 26 27 DIO21 CN4 27 28 DIO29 CN4 28 29 DIO20 CN4 29 30 DIO28 CN4 30 31 DIO19 CN4 31 32 DIO27 CN4 32 33 DIO18 CN4 33 34 DIO26 CN4 34 Table 8 IDAN DM35425 68 Pin Subminiature D Connector IDAN Pin Signal DM35425 Pin 35 DIO17 CN4 35 36 DIO25 CN4 ...

Page 21: ...served 20 Reserved 21 Reserved 22 AIN0 AIN8 CN3 2 23 AIN2 AIN2 CN3 5 24 AIN3 AIN11 CN3 8 25 AIN5 AIN5 CN3 11 26 AIN6 AIN14 CN3 14 27 AOUT0 CN3 17 28 AGND CN3 20 29 DIO7 CN3 23 30 DIO14 CN3 26 31 DIO4 CN3 29 Table 10 IDAN DM35425 62 Pin High Density D Connector IDAN Pin Signal DM35425 Pin 32 DIO11 CN3 32 33 DIO1 CN3 35 34 DIO8 CN3 38 35 EXT_CLK_3 CN3 41 36 EXT_CLK_6 CN3 44 37 Reserved CN3 47 38 GND...

Page 22: ...erved 21 Reserved 22 AIN8 AIN24 CN4 2 23 AIN10 AIN18 CN4 5 24 AIN11 AIN27 CN4 8 25 AIN13 AIN21 CN4 11 26 AIN14 AIN30 CN4 14 27 AOUT2 CN4 17 28 AGND CN4 20 29 DIO23 CN4 23 30 DIO30 CN4 26 31 DIO20 CN4 29 Table 10 IDAN DM35425 62 Pin High Density D Connector IDAN Pin Signal DM35425 Pin 32 DIO27 CN4 32 33 DIO17 CN4 35 34 DIO24 CN4 38 35 EXT_CLK_GATE3 CN4 41 36 EXT_CLK_GATE6 CN4 44 37 Reserved CN4 47 ...

Page 23: ... peripheral cards are connected to the cpuModule 6 Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack 7 Gently and evenly press the module onto the IDAN system 8 If any boards are to be stacked above this module install them 9 Finish assembling the IDAN stack by installing screws of an appropriate length 10 Attach any necessary cab...

Page 24: ... from the PCIe bus to the FPGA Each DMA channel also features a 64 bit PCI addressing and can access a maximum 16MB of memory for buffers 5 3 Analog input The DM35425 has 16 differential or 32 single end channel inputs muxed to a single 12 bit SAR ADC converter to provide high speed and high digital resolution of the analog input The ADC converter has a max throughput of 1 25MHz 1 Channel Refer to...

Page 25: ...s of operation Refer to section 6 3 16 for more information about FPGA registers Single Ended Input Mode In single ended mode the input signal is measured in reference to the boards GND In this mode the input signal is connected to input AIN0 through AIN31 and the low side to any of the GND pins available on the Analog Connector Differential Input Mode In this mode your signal source may or may no...

Page 26: ...B 2 500 V 0 MSB 0100 0000 000 LSB 0 000 V 0 MSB 0000 0000 0000 LSB 0 00244 V 1 MSB 1111 111 1111 LSB 5 000 V 1 MSB 1000 0000 0000 LSB Table 13 ADC Bipolar Code 10 V Input Range Input Voltages Sign Output Code 9 995 V 0 MSB 0111 1111 1111 LSB 5 000 V 0 MSB 0100 0000 000 LSB 0 000 V 0 MSB 0000 0000 0000 LSB 0 00488 V 1 MSB 1111 111 1111 LSB 10 000 V 1 MSB 1000 0000 0000 LSB Table 14 ADC Unipolar Cod...

Page 27: ...AC converter and begin sampling 1 Set the DAC to the Uninitialized state MODE Uninitialized 2 Setup the DMA for the channel 3 Set the input mode CH_FRONT_END_CONFIG 4 Set the start and stop triggers START_TRIG STOP_TRIG 5 Set the clock source CLK_SOURCE 6 Set the sample rate CLK_DIV_CNTR 7 Set the Post Capture counter POST_STOP_CAPTURE 8 Set the DAC to the Reset state MODE Reset 9 Start the DMA 10...

Page 28: ...DM35425 features 32 digital I O line with DMA parallel bus mode and advance interrupts DMA The DM35425 has three DMA channels for Digital I O input output and direction Each channel has a 511 sample FIFO for DMA Each sample is packed into 32 bits Advanced Interrupts The DM35425 has an advanced interrupt block that can generate an interrupt on a match or event The interrupts are across all 32 digit...

Page 29: ...ly on page 32 As an output CLK_SRC_GLBn will generated on the associated pin By default this signal will be a pulse that is high for 25ns when the CLK_SRC_GLBn signal goes high The width of this pulse can be increased using EXT_CLK_PWn Read Write on page 52 The following example show to capture ADC samples using an external and the external clocking function block External Clocking Function Block ...

Page 30: ...ritten to that bit to reset the register to 0 This is typically used for interrupt status registers Read Only This register can only be read NOTE Writing to Read Only registers may have unexpected results Clock Source Clock sources can serve as either sample clocks for function blocks or triggers for starting and stopping them Function blocks can drive a CLK_BUSn with a CLK_BUS_SRC see the registe...

Page 31: ...0x24 0x10 n FBn_OFFSET 0x28 0x10 n FBn_OFFSET_DMA 0x2C 0x10 n Reserved 0xA0 FB8_ID 0xA4 FB8_OFFSET 0xA8 FB8_OFFSET_DMA 0xAC Reserved 6 1 1 GBC_BRD_RST READ WRITE This register is used to send a reset command to the board Write 0xAA to this register to reset the board 6 1 2 GBC_EOI READ CLEAR This register is used to acknowledge an interrupt It is used to safeguard against missing an interrupt At t...

Page 32: ...the user clears it by writing a 1 to the appropriate bit 6 1 9 GBC_DIRQ_STATUS READ CLEAR This is a 64 bit interrupt status register for DMA interrupts Each bit in this register corresponds to one of the Function Blocks bit 0 corresponds to FB0 whose ID and OFFSET are at 0x020 etc Bits 60 through 63 are reserved This is a sticky register and the user clears it by writing a 1 to the appropriate bit...

Page 33: ...e overall control for this DMA channel After writing to the Action register the user should poll the Last_Action register below until it reads the same value This shows that the action has been performed by the DMA state machine This is especially important when entering and exiting the Clear state 0x00 Clear Clear the Current Buffer field the internal offset counters and the FIFO DMA is stopped 0...

Page 34: ...t to 1 by the DMA engine if it attempting to use a descriptor with the Valid bit cleared 6 2 6 FB_DMAM_STAT_OVERFLOW READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte Stat_Overflow will be set regardless of having ErrIntEna set to 1 If an overflow occurs the DMA engine will PAUSE B0 Overflow R C Set to 1 by the DMA engine i...

Page 35: ...ndicate that this contains valid information The DMA engine will set the error bit and halt if it is ready to use this descriptor and it is not valid B1 Halt Set to 1 to halt the DMA engine after this buffer is full B2 Loop Set to 1 to start back at descriptor 0 after this buffer is full This has a higher priority than the HALT bit B3 Interrupt Set to 1 to generate an interrupt after this buffer i...

Page 36: ... CLK_BUS2 Reserved FB 0x2C CLK_BUS7 CLK_BUS6 CLK_BUS5 CLK_BUS4 FB 0x30 Reserved ADC Channel 0 FB 0x34 CH0_FRONT_END_CONFIG Maskable register 16 bit FB 0x38 CH0_FIFO_DATA_CNT FB 0x3C CH0_THRESH_INT_ENA CH0_THRESH_INT_STAT CH0_FILTER Reserved FB 0x40 CH0_THRESH_LOW FB 0x44 CH0_THRESH_HIGH FB 0x48 CH0_LAST_SAMPLE ADC Channel 1 FB 0x4C CH1_FRONT_END_CONFIG Maskable register 16 bit FB 0x50 CH1_FIFO_DAT...

Page 37: ...d the FIFO is empty the triggering state machine is restarted i e FIFO is filled with Pre Start samples and waits for a start trigger B 7 4 Status o 0x08 Uninitialized The status when in the Uninitialized mode and the converter requires initialization o 0x09 Initializing o 0x00 Stopped The status when in the Reset mode or in the Uninitialized mode and the converter does not require initialization ...

Page 38: ...corresponds to an interrupt source A value of 1 enables the source and a value of 0 disables it See below for a description of the sources 6 3 14 INT_STAT READ CLEAR Each bit corresponds to an interrupt source Reading a value of 1 indicates that an event has occurred Reading a value of 0 indicates that the event has not occurred Writing a 1 will clear that bit B0 Sample A sample has been taken B1 ...

Page 39: ... Sample Clock Channel to Channel Delay o CH_DELAY 1 0 11 2 Full Sample Clock Channel to Channel Delay B 5 CH_ENABLE 0 Channel Disabled 1 Channel Enabled B 4 2 GAINSEL o GAINSEL 2 0 000 Gain of 1 o GAINSEL 2 0 001 Gain of 2 o GAINSEL 2 0 010 Gain of 4 o GAINSEL 2 0 011 Gain of 8 o GAINSEL 2 0 100 Gain of 0 5 B 1 BIP_UNI 0 Bipolar operation 1 Unipolar operation B 0 SE_ DIFF 0 Single Ended Input 1 Di...

Page 40: ...for the Threshold Detection Reading a 1 indicates that the threshold has been crossed Writing a 1 will clear the bit B0 1 Low Threshold has been crossed B1 1 High Threshold has been crossed 6 3 20 CHN_THRESH_ENA READ WRITE This is the interrupts enable for the threshold detection Bit defines are above An interrupt is generated if not already generated each time a sample is taken and the value is a...

Page 41: ...he 3 least significant bits are ignored from the actual threshold value NOTE The threshold value should not exceed the ADC range If the threshold value exceeds the ADC range unexpected results will occur 6 3 23 CHN_LAST_SAMPLE READ ONLY The last sample read from the ADC Converter after filtering This is the same value that is written to the DMA FIFO 6 3 24 CH_FIFO_ACCESS READ WRITE This register p...

Page 42: ..._FRONT_END_CONFIG Maskable register 16 bit FB 0x4C CH1_FIFO_DATA_CNT FB 0x50 CH1_ MARK_INT_ENA CH1_ MARK_INT_STAT Reserved Reserved FB 0x54 Reserved FB 0x58 CH1_LAST_ CONVERSION DAC Channel 2 FB 0x5C CH2_FRONT_END_CONFIG Maskable register 16 bit FB 0x60 CH2_FIFO_DATA_CNT FB 0x64 CH2_ MARK_INT_ENA CH2_ MARK_INT_STAT Reserved Reserved FB 0x68 Reserved FB 0x6C CH2_LAST_ CONVERSION DAC Channel 3 FB 0x...

Page 43: ...on o 0x01 Reserved o 0x02 Waiting for start trigger o 0x03 Converting Waiting for stop trigger o 0x04 Output Post Stop buffer o 0x05 Wait to re arm o 0x07 Done capturing 6 4 5 CLK_SRC READ WRITE Selects the source for CLK_DIV from the clock bus Refer to Clock Source on page 30 for list of valid values 6 4 6 START_TRIG READ WRITE Selects the start trigger from the clock bus CLK_DIV will start count...

Page 44: ...rce to drive onto Clock Bus N That clock bus can then be used by a different function block as a clock source or trigger A function block can drive multiple different Clock Buses However a Clock Bus N should not be driven by more than one function block at the same time or the clock signal will be undefined B 7 0 0x00 Disable Clock Source 0x80 Conversion A value has been sent 0x81 Channel Marker O...

Page 45: ...on software as to the state of the data being sent to the DAC Marker bit 7 corresponds to bit 31 of the DAC data and Marker bit 0 corresponds to bit 24 of the DAC data 6 4 18 CH_MARKER_ENA READ WRITE These are interrupts enables for the Data Markers Bit defines are above 6 4 19 CH_LAST_CONVERSION READ WRITE The last value sent to the DAC Converter B 31 24 DAC Markers B 12 0 DAC Data If the current...

Page 46: ...CESS DIO_IN FB 0x54 CH_FIFO_ACCESS DIO_OUT FB 0x58 CH_FIFO_ACCESS DIO_DIR 6 5 1 FB_ID READ ONLY This is the functional block ID This register should read 0x01003001 for the Advanced Digital I O functional block 6 5 2 FB_DMA_CHANNELS READ ONLY This register contains the number of DMA Channels in this Function Block Each Channel contains a control register and a set of Buffer Descriptor Registers 6 ...

Page 47: ...gger buffer can be filled o 0x07 Done capturing 6 5 5 CLK_SRC READ WRITE Selects the source for CLK_DIV from the clock bus Refer to Clock Source on page 30 for list of valid values 6 5 6 START_TRIG READ WRITE Selects the start trigger from the clock bus CLK_DIV will start counting after the start trigger Refer to Clock Source on page 30 for list of valid values 6 5 7 STOP_TRIG READ WRITE Selects t...

Page 48: ...ng a value of 1 indicates that an event has occurred Reading a value of 0 indicates that the event has not occurred Writing a 1 will clear that bit B0 Sample A sample has been taken B1 Advanced Int B2 Pre Start Buffer Filled B3 Start Trigger B4 Stop Trigger B5 Post Stop Buffer Filled B6 Sampling has completed and the FIFO is empty all data transferred to host B7 Pacer The pacer clock has ticked B8...

Page 49: ...36 DIO9 P_BUS_DATA9 8 38 DIO8 P_BUS_DATA8 7 23 DIO7 P_BUS_DATA7 6 25 DIO6 P_BUS_DATA6 5 27 DIO5 P_BUS_DATA5 4 29 DIO4 P_BUS_DATA4 3 31 DIO3 P_BUS_DATA3 2 33 DIO2 P_BUS_DATA2 1 35 DIO1 P_BUS_DATA1 0 37 DIO0 P_BUS_DATA0 6 5 17 DIO_OUTPUT READ WRITE The last value sent to the Digital I O Output If the current Mode is Reset or the associated DMA engine is set to Clear a write to this register will imm...

Page 50: ...ASK READ WRITE This register determines if a bit is checked for the advanced interrupts 0 Bit is used for match event 1 Bit is ignored 6 5 21 ADV_INT_COMP READ WRITE The compare register is used for the Match interrupt When all selected bits in this register match all selected bits on the DIO_INPUT register an interrupt is generated 6 5 22 ADV_INT_CAPT READ WRITE The Capture register latches the i...

Page 51: ...READ ONLY Has no DMA channels reads 0 6 6 3 FB_DMA_BUFFERS READ ONLY Has no DMA buffers reads 0 6 6 4 EXT_CLK_IN READ ONLY This register provides the current value on the External Clocking lines The bits in the register correspond with the External Clocking pins as follows Bit CN3 Pin Number CLK_BUSn Signal 5 45 7 EXT_CLK_7 4 44 6 EXT_CLK_6 3 43 5 EXT_CLK_5 2 42 4 EXT_CLK_4 1 41 3 EXT_CLK_3 0 39 2...

Page 52: ...or additional 25ns NOTE If EXT_CLK_PWn is set to be wider than the EXT_CLKn_CFG Clock Frequency the signal will just stay high 6 6 9 EXT_CLKN_CFG READ WRITE Selects clocking method B 7 0 0x00 Disables External Clocking 0x80 Not Gated EXT_CLKn will be inputted outputted independent of the EXT_CLK_GATEn corresponding gate value 0x81 Clock Gated High EXT_CLKn will be inputted when the EXT_CLK_GATEn c...

Page 53: ...can check the accuracy of your conversions using the procedure in this section and make adjustments as necessary Calibration is done with the module installed in your system Power up the system and let the DM35425HR circuitry stabilize for 15 minutes before calibration 7 1 Required Equipment The following equipment is required for calibration Precision voltage source 10 to 10 V Digital voltmeter 5...

Page 54: ... Bipolar 10 V Range Offset TR4 Input Voltage 1 22mV Converter Gain TR5 Input Voltage 4 99878V ADC Converted Data 0000 0000 0000 1000 0000 0000 1111 1111 1111 1000 0000 0001 Bipolar Range Adjustment 10 to 10 V To adjust the bipolar 20 V range 10 to 10 V program the board for 10 V input range Then set the input voltage to 5 0000 V and adjust TR2 until the output matches the data in the table below T...

Page 55: ...a table listing the ideal input voltage for each bit weight for the unipolar ranges Table 27 ADC Bit Weights Unipolar Sign ADC Bit Weight Ideal Output Voltage mV 0 to 10 V 0 1111 1111 1111 9997 60 0 1000 0000 0000 5000 00 0 0100 0000 0000 2500 00 0 0010 0000 0000 1250 00 0 0001 0000 0000 625 00 0 0000 1000 0000 312 50 0 0000 0100 0000 156 25 0 0000 0010 0000 78 13 0 0000 0001 0000 39 06 0 0000 000...

Page 56: ...56 1000 0000 0000 0 2500 00 0000 00 5000 00 0100 0000 0000 2500 00 1250 00 5000 00 2500 00 0010 0000 0000 3750 00 625 00 7500 00 1250 00 0001 0000 0000 4375 00 312 50 8750 00 625 00 0000 1000 0000 4687 50 156 25 9375 00 312 50 0000 0100 0000 4843 75 78 13 9687 50 156 25 0000 0010 0000 4921 88 39 06 9843 75 78 13 0000 0001 0000 4960 94 19 53 9921 88 39 06 0000 0000 1000 4980 47 9 77 9960 94 19 53 0...

Page 57: ...ast number of modules in the system possible Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly If problems persist or you have questions about configuring this product contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E Mail techsupport rtd com Be sure to ...

Page 58: ...Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium www pc104 org 9 2 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group www pcisig com ...

Page 59: ...r other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims al...

Page 60: ...nologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Copyright 2017 by RTD Embedded Technologies Inc All rights reserved ...

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