rtd cpuModule CMX47786HX, User Manual

Page: 83 / 108

CMX47786HX RTD Embedded Technologies, Inc.
75
Watchdog Timer Control
The cpuModule includes a Watchdog Timer, which provides protection against programs “hang-
ing”, or getting stuck in an execution loop where they cannot respond correctly. The watchdog timer
consists of a counter, a reset generator, and an interrupt generator. When the counter reaches the
interrupt time-out, it can generate an interrupt. When the counter reaches the reset time-out, the sys-
tem is reset. The counter is “refreshed,” or set back to zero by reading from a specific register. The
watchdog can also be put into an “inactive” state, in which no resets or interrupts are generated.
The ability to generate an interrupt allows the application to gracefully recover from a bad state. For
example, consider a system that has a reset time-out of 2 seconds, interrupt time-out of 1 second, and
the watchdog timer is refreshed every 0.5 seconds. If something goes wrong, an interrupt is gener-
ated. The Interrupt service routine then attempts to restart the application software. If it is success-
ful, the application is restarted in much less time than a full reboot would require. If it is not
successful, the system is rebooted.
Due to system latency, it is recommended that the Watchdog be refreshed at about half of the reset
time-out period, or half of the interrupt time-out period, whichever is applicable.
Register Description
The Advanced Watchdog Timer has two Setup Registers and a Runtime Register. The Setup Reg-
isters are set by the BIOS, and can be adjusted by entering the BIOS Setup Utility, and going to In-
tegrated Peripherals. See
Configuring with the RTD Enhanced Award BIOS on page 56 for more
details. The Setup Register may also be read by the driver to determine if the Watchdog is enabled,
and the interrupt and base address that it is using.
In the following register description sections, each register is described by a register table. The first
row of the table list the bits, D7 through D0. The second row lists the field name for each bit. The
third row lists the properties of that bit; ‘r’ = bit can be read, ‘w’ = bit can be written to, and ‘c’ = bit
can be cleared. The last row lists the value of the bit after reset. The register table is then followed
by a description of each of the fields where applicable.
Advanced Watchdog Setup Register (I/O Port 0x18)
WDT_IRQ[2:0] Selects the Interrupt assigned to the Watchdog Timer.
WDT_Setup
D7 D6 D5 D4 D3 D1 D0
Reserved Reserved Reserved Reserved WDT_IRQ Reg_Enable
r r r r r/w r/w
0 0 0 0 0 0
WDT_IRQ[2:0] Interrupt
000 DIsabled.
001 IRQ5
010 IRQ7
011 IRQ10
100 IRQ11