Rohm Kionix KX132-1211, Technical Reference Manual

Page: 36 / 73

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. – Ithaca, NY 14850 © 2019 Kionix – All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146 893-12874-1907311402-0.17
www.kionix.com - info@kionix.com Page 36 of 73
TWS
This register contains counter information for the detection of single and double taps. When the Directional-Tap
TM
ODR
is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional-Tap
TM
ODR is 800Hz, every
count is calculated as 2/ODR delay period. When the Directional-Tap
TM
ODR is 1600Hz, every count is calculated as
4/ODR delay period. The Directional-Tap
TM
ODR is user-defined per Table 10. It defines the time window for the entire
tap event, single or double, to occur. Reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the
end of this tap window. The Kionix recommended default value for TWS is 0.4 seconds (0xA0).
R/W R/W R/W R/W R/W R/W R/W R/W
TWS7 TWS6 TWS5 TWS4 TWS3 TWS2 TWS1 TWS0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10100000
Address: 0x31
1.17 FREE FALL CONTROL REGISTERS (0x32
– 0x34)
The Free fall engine is enabled with FFIE bit in FFCNTL register and can be configured via control registers 0x32
–
0x34. Please refer to Free fall Detect section for detailed information on the Free fall engine.
FFTH
Free Fall Threshold. This register contains the threshold of the Free fall detection. This value is compared to the top 8
bits of the accelerometer 8g output (independent of the actual g-range setting of the device). This register is On-The-
Fly (OTF) register and can be written to while the KX132-1211 is enabled
(PC1 bit in CNTL1 register is set to “1”) and
the change will be accepted with no interruption in the operation.
R/W R/W R/W R/W R/W R/W R/W R/W
FFTH7 FFTH6 FFTH5 FFTH4 FFTH3 FFTH2 FFTH1 FFTH0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000
Address: 0x32
FFC
Free Fall Counter. This register contains the counter setting of the Free fall detection. Every count is calculated as
1/ODR delay period where ODR is set bit OFFI<2:0> in FFCNTL register. This register is On-The-Fly (OTF) register
and can be written to while the KX132-1211
is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be
accepted with no interruption in the operation.
R/W R/W R/W R/W R/W R/W R/W R/W
FFC7 FFC6 FFC5 FFC4 FFC3 FFC2 FFC1 FFC0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000
Address: 0x33