± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146
893-12874-1907311402-0.17
www.kionix.com -
Page
31
of
73
INC5
Interrupt Control 5. This register controls the settings for the physical interrupt pin INT2. Note that to properly change
the value of this register, the PC1 bit in CNTL1 register
must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PW21
PW20
IEN2
IEA2
IEL2
Reserved
ACLR2
ACLR1
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00010000
Address:
0x26
PW2<1:0>
– Pulse INT2 pin width configuration
00 = 50µsec (10µsec if accelerometer ODR (OSA<3:0>) > 1600Hz)
01 = 1 * OSA period
10 = 2 * OSA periods
11 = Real time mode
When PW2 > 0, Interrupt source auto-clearing (ACLR2=1) should be set to keep consistency
between the internal status and the physical interrupt.
IEN2
– enables/disables the physical interrupt pin
IEN2 = 0
– physical interrupt pin is disabled
IEN2 = 1
– physical interrupt pin is enabled
IEA2
– Interrupt active level control for interrupt pin
IEA2 = 0
– active LOW
IEA2 = 1
– active HIGH
IEL2
– Interrupt latch control for interrupt pin
IEL2 = 0
– latched
IEL2 = 1
– pulsed. The pulse width is configurable by PW2.
Reserved
– this bit is reserved, and its value should not be changed.
ACLR2
– Latched interrupt source information (INS1-INS3) is cleared and physical interrupt-2 latched
pin is changed to its inactive state at pulse interrupt-2 trailing edge. Note: WMI and BFI are not
auto-cleared by a pulse interrupt trailing edge.
ACLR2 = 0
– disable
ACLR2 = 1
– enable
ACLR1
– Latched interrupt source information (INS1-INS3) is cleared and physical interrupt-1 latched
pin is changed to its inactive state at pulse interrupt-1 trailing edge. Note: WMI and BFI are not
auto-cleared by a pulse interrupt trailing edge.
ACLR1 = 0
– disable
ACLR1 = 1
– enable
