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© 2022 ROHM Co., Ltd.
65UG028E Rev.001
2022.7
User's Guide
BD7F105EFJ-EVK-001
Application Design Examples-continued
R
FB
has been decided, let's decide the winding ratios of the other output transformers.
Since Np/Ns1 is 0.92, we designed Np=11T and Ns1=12T.
At this time, the formula for output voltage 2 is as follows.
𝑉
𝑂𝑈𝑇
=
𝑅
𝐹𝐵
𝑅
𝑅𝐸𝐹
×
𝑁
𝑆2
𝑁
𝑃
× 𝑉
𝐼𝑁𝑇𝑅𝐸𝐹
− 𝑉
𝐹
Therefore, Ns2=31T. Determine Ns3 as 12T by the same formula.
3.
Output Capacitor
Place the output capacitor as close to the secondary diode as possible.
The output capacitance value C
OUT
is set from the output ripple voltage ΔV
O
and the start-up time.
The output ripple voltage generated by one switching is calculated as follows.
𝛥𝑉
𝑂
=
𝐼
𝑂𝑈𝑇(𝑀𝑎𝑥)
× 𝐷
𝑀𝐴𝑋
𝑓
𝑆𝑊(𝑀𝑎𝑥)
× 𝐶
𝑂𝑈𝑇
On the other hand, when output capacitor is large, start-up time is long.
When SCP detection mask time (t
MASKSCP
) in start-up is passed, if REF voltage is lower than V
SCP
, power supply cannot
output. Therefore, C
OUT
must be satisfied below condition.
𝐶
𝑂𝑈𝑇
≤
1
2
×
𝑡
𝑀𝐴𝑆𝐾𝑆𝐶𝑃(𝑀𝑖𝑛)
× {(𝐼
𝐿𝐼𝑀𝐼𝑇(𝑀𝑖𝑛)
×
𝑁
𝑃
𝑁
𝑆
) × (1 − 𝐷𝑢𝑡𝑦) − 𝐼
𝑂𝑈𝑇(𝑀𝑎𝑥)
}
𝑉
𝑂𝑈𝑇
× (
𝑉
𝑆𝐶𝑃(𝑀𝑎𝑥)
𝑉
𝐼𝑁𝑇𝑅𝐸𝐹(𝑀𝑖𝑛)
)
Where
𝑉
𝑆𝐶𝑃(𝑀𝑎𝑥)
𝑉
𝐼𝑁𝑇𝑅𝐸𝐹(𝑀𝑖𝑛)
= 0.762
A large capacitor capacitance value is required to hold the output voltage during load response or power supply
voltage response.
A capacitance value of 20 μF or more is recommended as a guideline for the output voltage capacitance.
Ceramic capacitors are affected by temperature characteristics, capacitance variation, DC bias characteristics, etc.
The capacitance value may decrease. Pay attention to these points when selecting parts.
4. Input Capacitor
Use a ceramic capacitor for the input capacitor and place it as close to the IC as possible.
Capacitance of the capacitor should be 10 μF or more.
[V]
[µF]
