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Richtek RT8884B Manual Download Page 39

RT8884B

39

DS8884B-01   September  2013

www.richtek.com

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Copyright   2013 Richtek Technology Corporation. All rights reserved.                          is a registered trademark of Richtek Technology Corporation.

Figure 21. Remote Sensing Circuit

CPU V

CC_SENSE

-

+

FB

RGND

EA

-

+

VID

R1

CPU V

SS_SENSE

R2

V

OUT

C

OUT

Precise Reference Current Generation, IBIAS

Analog circuits need very precise reference voltage/current
to drive/set these analog devices. The RT8884B provides
a 2V voltage source at the IBIAS pin, and a 100k

Ω

 resistor

is required to be connected between the IBIAS pin and
analog ground to generate a very precise reference current.
Through this connection, the RT8884B will generate a
20

μ

A current from the IBIAS pin to analog ground, and

this 20

μ

A current will be mirrored inside the RT8884B for

internal use. The IBIAS pin can only be connected with a
100k

Ω

 resistor to GND for internal analog circuit use. The

resistance accuracy of this resistor is recommended to
be 1% or higher. Figure 19 shows the IBIAS setting circuit.

Figure 19. IBIAS Setting Circuit

TSEN

CC

NTC(100 C)

R2

V

 = V

 = 1.887V

R2 +  R1//R

°

×

⎡

⎤

⎣

⎦

+

-

IBIAS

100k

Current Mirror

2V

20µA

Figure 20. VR_HOT Circuit

Differential Remote Sense Setting

The VR provides differential remote sense inputs to
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts.
The CPU contains on-die sense pins, V

CC_SENSE

 and

V

SS_SENSE

. Connecting RGND to V

SS_SENSE

 and FB to

V

CC_SENSE

 with a resistor to build the negative input path

of the error amplifier. The V

DAC

 and the precision voltage

reference are referred to RGND for accurate remote
sensing.

TSEN

R1

R2

NTC

+

-

1.887V

VDDIO

VR_HOT

VCC

TSEN and VR_HOT

The VR_HOT signal is an open-drain signal which is used
for VR thermal protection. When the sensed voltage in
TSEN pin is over 1.887V, the VR_HOT signal will be pulled-
low to notify CPU that the thermal protection needs to
work. According to Intel VR definition, VR_HOT signal
needs acting if VR power chain temperature exceeds
100

°

C. Placing an NTC thermistor at the hottest area in

the VR power chain and its connection is shown in Figure
20, to design the voltage divider elements (R1, R2 and
NTC) so that VTSEN = 1.887V at 100

°

C. The resistance

accuracy of TSEN network is recommended to be 1% or
higher.

Summary of Contents for RT8884B

Page 1: ...ing states A Serial VID SVID interface is built in the RT8884B to communicate with Intel VR12 5 compliant CPU The RT8884B supports VID on the fly function with three different slew rates Fast Slow and Decay By utilizing the G NAVPTM topology the operating frequency of the RT8884B varies with VID load current and input voltage to further enhance the efficiency even in CCM Besides G NAVPTM the CCRCO...

Page 2: ... of IPC JEDEC J STD 020 Suitable for use in SnPb or Pb free soldering processes Marking Information 0F Product Code YMDNN Date Code Package Type QW WQFN 32L 4x4 W Type RT8884B Lead Plating System G Green Halogen Free and Pb Free 0F YM DNN ISEN1P ISEN4N ISEN3N ISEN3P DVD VCLK TONSET VR_RDY VSEN RGND VCC SET1 ISEN2N ISEN2P EN PWM2 IMON ISEN4P VDIO ALERT FB ISEN1N SET2 PWM1 VREF VR_HOT SET3 PWM3 IBIA...

Page 3: ...nnect this pin to 5V and place a minimum 2 2μF decoupling capacitor The decoupling capacitor should be placed to this pin as close as possible 13 SET1 1 st Platform Setting Platform can use this pin to set DVID time RSET DVID width and OCS 14 SET2 2 nd Platform Setting Platform can use this pin to set ICCMAX QRTH and QRSET 15 SET3 3 rd Platform Setting Platform can use this to set output offset vo...

Page 4: ...Cancellation ISEN4P ISEN3N ISEN3P ISEN2N ISEN2P ISEN1N ISEN1P Current Balance To Protection Logic DAC TON GEN Current mirror IB1 Current mirror IB2 Current mirror IB3 Current mirror IB4 OCS OC VSEN IMON VREF PWM CMP QR_TH QRWIDTH RSET TONSET SET2 Loop Control Protection Logic SVID Interface Configuration Registers Control Logic UVLO TON QR_TH QRWIDTH ADC SET1 IMONI TSEN EN DVD VCC VR_RDY GND MUX V...

Page 5: ...ng to the phase control signal from the Loop Control Protection Logic SVID Interface Configuration Registers Control Logic The interface that receives the SVIDsignal from CPU and sends the relative signals to Loop Control Protection Logic to execute the action by CPU The registers save the pin setting data from ADC output The Control Logic controls theADC timing and generates the digital code of t...

Page 6: ...0 0 0 0 0 1 1 0 0 0C 0 610 0 0 0 0 1 1 0 1 0D 0 620 0 0 0 0 1 1 1 0 0E 0 630 0 0 0 0 1 1 1 1 0F 0 640 0 0 0 1 0 0 0 0 10 0 650 0 0 0 1 0 0 0 1 11 0 660 0 0 0 1 0 0 1 0 12 0 670 0 0 0 1 0 0 1 1 13 0 680 0 0 0 1 0 1 0 0 14 0 690 0 0 0 1 0 1 0 1 15 0 700 0 0 0 1 0 1 1 0 16 0 710 0 0 0 1 0 1 1 1 17 0 720 0 0 0 1 1 0 0 0 18 0 730 0 0 0 1 1 0 0 1 19 0 740 0 0 0 1 1 0 1 0 1A 0 750 0 0 0 1 1 0 1 1 1B 0 76...

Page 7: ...0 0 1 1 33 1 000 0 0 1 1 0 1 0 0 34 1 010 0 0 1 1 0 1 0 1 35 1 020 0 0 1 1 0 1 1 0 36 1 030 0 0 1 1 0 1 1 1 37 1 040 0 0 1 1 1 0 0 0 38 1 050 0 0 1 1 1 0 0 1 39 1 060 0 0 1 1 1 0 1 0 3A 1 070 0 0 1 1 1 0 1 1 3B 1 080 0 0 1 1 1 1 0 0 3C 1 090 0 0 1 1 1 1 0 1 3D 1 100 0 0 1 1 1 1 1 0 3E 1 110 0 0 1 1 1 1 1 1 3F 1 120 0 1 0 0 0 0 0 0 40 1 130 0 1 0 0 0 0 0 1 41 1 140 0 1 0 0 0 0 1 0 42 1 150 0 1 0 0 ...

Page 8: ...1 0 1 1 5B 1 400 0 1 0 1 1 1 0 0 5C 1 410 0 1 0 1 1 1 0 1 5D 1 420 0 1 0 1 1 1 1 0 5E 1 430 0 1 0 1 1 1 1 1 5F 1 440 0 1 1 0 0 0 0 0 60 1 450 0 1 1 0 0 0 0 1 61 1 460 0 1 1 0 0 0 1 0 62 1 470 0 1 1 0 0 0 1 1 63 1 480 0 1 1 0 0 1 0 0 64 1 490 0 1 1 0 0 1 0 1 65 1 500 0 1 1 0 0 1 1 0 66 1 510 0 1 1 0 0 1 1 1 67 1 520 0 1 1 0 1 0 0 0 68 1 530 0 1 1 0 1 0 0 1 69 1 540 0 1 1 0 1 0 1 0 6A 1 550 0 1 1 0 ...

Page 9: ...0 0 1 1 83 1 800 1 0 0 0 0 1 0 0 84 1 810 1 0 0 0 0 1 0 1 85 1 820 1 0 0 0 0 1 1 0 86 1 830 1 0 0 0 0 1 1 1 87 1 840 1 0 0 0 1 0 0 0 88 1 850 1 0 0 0 1 0 0 1 89 1 860 1 0 0 0 1 0 1 0 8A 1 870 1 0 0 0 1 0 1 1 8B 1 880 1 0 0 0 1 1 0 0 8C 1 890 1 0 0 0 1 1 0 1 8D 1 900 1 0 0 0 1 1 1 0 8E 1 910 1 0 0 0 1 1 1 1 8F 1 920 1 0 0 1 0 0 0 0 90 1 930 1 0 0 1 0 0 0 1 91 1 940 1 0 0 1 0 0 1 0 92 1 950 1 0 0 1 ...

Page 10: ... 1 0 1 1 AB 2 200 1 0 1 0 1 1 0 0 AC 2 210 1 0 1 0 1 1 0 1 AD 2 220 1 0 1 0 1 1 1 0 AE 2 230 1 0 1 0 1 1 1 1 AF 2 240 1 0 1 1 0 0 0 0 B0 2 250 1 0 1 1 0 0 0 1 B1 2 260 1 0 1 1 0 0 1 0 B2 2 270 1 0 1 1 0 0 1 1 B3 2 280 1 0 1 1 0 1 0 0 B4 2 290 1 0 1 1 0 1 0 1 B5 2 300 1 0 1 1 0 1 1 0 B6 2 310 1 0 1 1 0 1 1 1 B7 2 320 1 0 1 1 1 0 0 0 B8 2 330 1 0 1 1 1 0 0 1 B9 2 340 1 0 1 1 1 0 1 0 BA 2 350 1 0 1 1...

Page 11: ... 0 0 1 1 D3 2 600 1 1 0 1 0 1 0 0 D4 2 610 1 1 0 1 0 1 0 1 D5 2 620 1 1 0 1 0 1 1 0 D6 2 630 1 1 0 1 0 1 1 1 D7 2 640 1 1 0 1 1 0 0 0 D8 2 650 1 1 0 1 1 0 0 1 D9 2 660 1 1 0 1 1 0 1 0 DA 2 670 1 1 0 1 1 0 1 1 DB 2 680 1 1 0 1 1 1 0 0 DC 2 690 1 1 0 1 1 1 0 1 DD 2 700 1 1 0 1 1 1 1 0 DE 2 710 1 1 0 1 1 1 1 1 DF 2 720 1 1 1 0 0 0 0 0 E0 2 730 1 1 1 0 0 0 0 1 E1 2 740 1 1 1 0 0 0 1 0 E2 2 750 1 1 1 0...

Page 12: ...ID0 HEX Voltage V 1 1 1 1 0 0 0 0 F0 2 890 1 1 1 1 0 0 0 1 F1 2 900 1 1 1 1 0 0 1 0 F2 2 910 1 1 1 1 0 0 1 1 F3 2 920 1 1 1 1 0 1 0 0 F4 2 930 1 1 1 1 0 1 0 1 F5 2 940 1 1 1 1 0 1 1 0 F6 2 950 1 1 1 1 0 1 1 1 F7 2 960 1 1 1 1 1 0 0 0 F8 2 970 1 1 1 1 1 0 0 1 F9 2 980 1 1 1 1 1 0 1 0 FA 2 990 1 1 1 1 1 0 1 1 FB 3 000 1 1 1 1 1 1 0 0 FC 3 010 1 1 1 1 1 1 0 1 FD 3 020 1 1 1 1 1 1 1 0 FE 3 030 1 1 1 1...

Page 13: ...s not control the slew rate The output voltage decays at a rate proportional to the load current 2 Low side MOSFET is not allowed to sync current 3 ACK 11b when target higher than current VOUT voltage 4 ACK 10b when target lower than current VOUT voltage 04h SetPS Byte indicating power states N A 1 Set power state 2 ACK 11b when not support 3 ACK 10b even slave not change configuration 4 ACK 11b f...

Page 14: ... the status_2 R M W PWM 00h 21h ICC Max Data register containing the ICC max the platform supports Binary format in A IE 64h 100A RO Platform 7Dh 22h Temp Max Data register containing the temperature max the platform supports Binary format in C IE 64h 100 C RO Platform 64h 24h SR fast Data register containing the capability of fast slew rate the platform can sustain Binary format in mV μs IE 0Ah 1...

Page 15: ...27 8 C W WQFN 32L 4x4 θJC 7 C W Junction Temperature 150 C Lead Temperature Soldering 10 sec 260 C Storage Temperature Range 65 C to 150 C ESD Susceptibility Note 3 HBM Human Body Model 2kV VCC 5V TA 25 C unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current IVCC VEN H Not switching 4 1 mA Supply Current at PS3 IVCC_PS3 VEN H Not switching 2 7 mA ...

Page 16: ...1 7V 450 500 550 ns Input Current Range IRTON VDAC 1 7V 25 280 μA Minimum Off time TOFF VDAC 1 7V 400 ns IBIAS IBIAS Pin Voltage VIBIAS RIBIAS 100kΩ 1 85 2 V OFS Setting Impedance ROFS 1 MΩ Enable OFS function and offset 600mV 1 95 2 4 2 44 Enable OFS function and offset 300mV 1 76 1 8 1 84 Enable OFS function and offset 0V 1 16 1 2 1 24 Enable OFS function and offset 50mV 1 06 1 1 1 14 Enable OFS...

Page 17: ... 6 0 65 V VBOOT Voltage VBOOT No Load set VBOOT 1 7V 1 692 1 7 1 708 V ADC VIMON VIMON_INI 1 6V 252 255 258 VIMON VIMON_INI 0 8V 125 128 131 Digital IMON Set VIMON VIMON VIMON_INI 0V 0 0 3 Decimal Update Period of IMON TIMON 320 400 480 μs TSEN Threshold for Tmp_Zone 7 transition VTSEN 100 C 1 887 V TSEN Threshold for Tmp_Zone 6 transition VTSEN 97 C 1 837 V TSEN Threshold for Tmp_Zone 5 transitio...

Page 18: ...e indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions may affect device reliability Note 2 θJA is measured at TA 25 C on a high effective thermal conductivity four layer test board per JEDEC 51 7 θJC is measured at the exposed pad of the package Note 3 Devices are ESD sensitive Handling precaution is recommended Note 4 The devic...

Page 19: ...5 6k 100k C5 390pF C6 90pF R24 10k C7 C8 C9 Optional Optional Optional R19 10k R20 75 R21 130 R22 130 R23 150 R18 5 43k 100k R16 12 6k C4 0 47µF R17 13 9k R15 100k R13 1 C3 0 1µF R49 680 Q8 x 2 Q7 R45 0 R44 2 2 C32 0 1µF C33 22µF C34 390µF C36 1µF R47 510 Optional R48 R46 C35 Optional R43 680 Q6 x 2 Q5 R39 0 R38 2 2 C26 0 1µF C27 22µF C28 390µF C30 1µF R41 510 Optional R42 R40 C29 Optional R37 680...

Page 20: ...7V Time 200μs Div CORE VR Power Off from EN EN 2V Div VR_RDY 2V Div UGATE1 20V Div VCORE 2V Div VIN 12V VID 1 85V to 1 6V Slew Rate Slow Time 20μs Div CORE VR Dynamic VID Down VCLK 2V Div VDIO 2V Div ALERT 2V Div VCORE 1V Div VIN 12V VID 1 6V to 1 85V Slew Rate Slow Time 20μs Div CORE VR Dynamic VID Up VCLK 2V Div VDIO 2V Div ALERT 2V Div VCORE 1V Div VIN 12V Boot VID 1 7V Time 40μs Div CORE VR OV...

Page 21: ...EN 1V Div VR_HOT 1V Div VIN 12V VID 1 6V to 1 85V Slew Rate Fast Time 10μs Div CORE VR Dynamic VID Up VCLK 2V Div VDIO 2V Div ALERT 2V Div VCORE 1V Div VIN 12V VID 1 85V to 1 6V Slew Rate Fast Time 10μs Div CORE VR Dynamic VID Down VCLK 2V Div VDIO 2V Div ALERT 2V Div VCORE 1V Div VIN 12V VID 1 7V PS2 to PS0 ILOAD 0 6A Time 100μs Div CORE VR Mode Transient VCLK 1V Div UGATE1 20V Div LGATE1 10V Div...

Page 22: ...y State Figure 1 b G NAVPTM Behavior Waveforms in CCM in Load Transient PWM1 PWM2 PWM3 PWM4 Current feedback signal Comp signal PWM1 PWM2 PWM3 PWM4 Current feedback signal Comp signal Diode Emulation Mode DEM As well known the dominate power loss is switching related loss during light load hence VR needs to be operated in asynchronous mode or called discontinuous conduct mode DCM to reduce switchi...

Page 23: ...DEM in Steady State Figure 3 G NAVPTM Operation in DEM Inductor current Phase node UGATE LGATE Output capacitor discharge slope UGATE LGATE COMP signal Inductor current signal a Lighter Load Condition Capacitor discharge slope is lower than Figure 3 b Output capacitor discharge slope UGATE LGATE COMP signal Inductor current signal b Load Increased Condition Capacitor discharge slope is higher than...

Page 24: ...nal current sense method requiring aNTC resistor in per phase current loop for thermal compensation RT8884B adopts the total current sense method requiring only oneNTC resistor for thermal compensation andNTC resistor cost can be saved by using this method Figure 5 shows the total current sense method which connecting the resistor network between the IMONand VREF pins to set a part of current loop...

Page 25: ... type II or type III compensator to optimize control loop performance It can adopt a simple type I compensator one pole one zero in G NAVPTM topology to achieve constant output impedance design for Intel VR12 5 ACLL specification The one pole one zero compensator is shown as Figure 8 the transfer function of compensator should be designed as the following transfer function to achieve constant outp...

Page 26: ...ted as follows Function 1 CC Function 2 R2 V V R1 R2 R1 R2 V 80 A R1 R2 μ All function setting will be done within 500μs after power ready POR If VFunction 1 and VFunction 2 are determined R1 and R2 can be calculated as follows Figure 9 Multi Function Pin Setting Mechanism Connecting a R3 resistor from SET 1 2 pin to the middle node of voltage divider can help to fine tune the set voltage of Funct...

Page 27: ...his setting accuracy 1 error tolerance is recommended In the Table 4 there are some No Use marks in QRWIDTH section It means that user should not use it to avoid the possibility of shift digital code due to tolerance concern Figure 10 Multi Function Pin Setting Mechanism with a R3 Resistor to Fine Tune the Set Voltage of Function 2 Quick Response QR Mechanism When the transient load step up become...

Page 28: ... 325 318 336 266 347 214 mV 101 67 350 342 361 290 372 239 mV 110 44 375 367 386 315 397 263 mV 001 111 30mV No Use 400 391 411 339 422 287 mV 000 No Use 425 415 436 364 447 312 mV 001 155 450 440 461 388 472 336 mV 010 133 475 464 486 413 497 361 mV 011 111 500 489 511 437 522 385 mV 100 89 525 513 536 461 547 410 mV 101 67 550 538 561 486 572 434 mV 110 44 575 562 586 510 597 458 mV 010 111 35mV...

Page 29: ... effect A virtual charge current signal is established first and then VID signal plus virtual charge current signal is generated in FB pin Hence an induced charge current signal flows to R1 and is cancelled to reduce droop effect QR_SET R1 R2 V 80 A R1 R2 μ Min Typical Max unit QR_TH 2 0 QRWIDTH 2 0 QR Threshold QR Width TON 1000 978 1011 926 1022 874 mV 000 No Use 1026 002 1036 950 1047 898 mV 00...

Page 30: ...Charge Current Slew Rate Control Virtual Charge Current Generator DVID Event SET1 DVID_Threshold DVID_Width Figure 15 Definition of Virtual Charge Current Signal Table 5 and Table 6 show the DVID_Threshold and DVID_Width settings in SET1 pin For example 25mV DVID_Threshold and 72μsDVID_Width are designed OCP sets as 100 ICCMAX and RSET sets as 100 Ramp current The DVID_Width is set by an external ...

Page 31: ... 336 266 347 214 mV 101 140 350 342 361 290 372 239 mV 110 150 375 367 386 315 397 263 mV 001 111 25mV No Use 400 391 411 339 422 287 mV 000 No Use 425 415 436 364 447 312 mV 001 100 450 440 461 388 472 336 mV 010 110 475 464 486 413 497 361 mV 011 120 500 489 511 437 522 385 mV 100 130 525 513 536 461 547 410 mV 101 140 550 538 561 486 572 434 mV 110 150 575 562 586 510 597 458 mV 010 111 35mV No...

Page 32: ...124 1162 072 1173 021 mV 110 150 1176 149 1187 097 1198 045 mV 101 111 65mV No Use 1201 173 1212 121 1223 069 mV 000 No Use 1226 197 1237 146 1248 094 mV 001 100 1251 222 1262 170 1273 118 mV 010 110 1276 246 1287 195 1298 143 mV 011 120 1301 271 1312 219 1323 167 mV 100 130 1326 295 1337 243 1348 192 mV 101 140 1351 320 1362 268 1373 216 mV 110 150 1376 344 1387 292 1398 240 mV 110 111 75mV No Us...

Page 33: ... 214 mV 101 125 350 342 361 290 372 239 mV 110 137 5 375 367 386 315 397 263 mV 001 111 72μs No Use 400 391 411 339 422 287 mV 000 No Use 425 415 436 364 447 312 mV 001 75 450 440 461 388 472 336 mV 010 87 50 475 464 486 413 497 361 mV 011 100 500 489 511 437 522 385 mV 100 112 5 525 513 536 461 547 410 mV 101 125 550 538 561 486 572 434 mV 110 137 5 575 562 586 510 597 458 mV 010 111 96μs No Use ...

Page 34: ...72 1173 021 mV 110 137 5 1176 149 1187 097 1198 045 mV 101 111 168μs No Use 1201 173 1212 121 1223 069 mV 000 No Use 1226 197 1237 146 1248 094 mV 001 75 1251 222 1262 170 1273 118 mV 010 87 5 1276 246 1287 195 1298 143 mV 011 100 1301 271 1312 219 1323 167 mV 100 112 5 1326 295 1337 243 1348 192 mV 101 125 1351 320 1362 268 1373 216 mV 110 137 5 1376 344 1387 292 1398 240 mV 110 111 192μs No Use ...

Page 35: ...etween RTON and ramp compensation For example when designed RTON is 100kΩ the RAMP is set as IMON REF EQ L1 L2 L3 L4 CS DCR V V R I I I I R Where IL1 IL2 IL3 IL4 are output current and the definitions of DCR RCS and REQ can refer to Figure 6 Maximum Processor Current Setting ICCMAX The maximum processor current ICCMAX can be set by the SET2 pin ICCMAX register is set by an external voltage divider...

Page 36: ...4 184 mV 70 A 450 440 453 568 456 696 mV 72 A 462 952 466 080 469 208 mV 74 A 475 464 478 592 481 720 mV 76 A 487 977 491 105 494 233 mV 78 A 500 489 503 617 506 745 mV 80 A ICCMAX CC R2 V V R1 R2 Min Typical Max Unit ICCMAX Unit 513 001 516 129 519 257 mV 82 A 525 513 528 641 531 769 mV 84 A 538 025 541 153 544 282 mV 86 A 550 538 553 666 556 794 mV 88 A 563 050 566 178 569 306 mV 90 A 575 562 57...

Page 37: ... mV 198 A 1251 222 1254 350 1257 478 mV 200 A 1263 734 1266 862 1269 990 mV 202 A 1276 246 1279 374 1282 502 mV 204 A 1288 759 1291 887 1295 015 mV 206 A 1301 271 1304 399 1307 527 mV 208 A ICCMAX CC R2 V V R1 R2 Min Typical Max Unit ICCMAX Unit 1313 783 1316 911 1320 039 mV 210 A 1326 295 1329 423 1332 551 mV 212 A 1338 807 1341 935 1345 064 mV 214 A 1351 320 1354 448 1357 576 mV 216 A 1363 832 1...

Page 38: ... NVP triggering The NVP function will be active only after OVP is triggered Under Voltage Protection When the VSEN pin voltage is 350mV less than VID a UVP will be latched When UVP latched both the UGATEx and LGATEx will be pulled low A 3μs delay is used in UVP detection circuit to prevent false trigger Besides the UVP function is masked when dynamic VID transient occurs and after dynamic VID tran...

Page 39: ...t TSEN CC NTC 100 C R2 V V 1 887V R2 R1 R IBIAS 100k Current Mirror 2V 20µA Figure 20 VR_HOT Circuit Differential Remote Sense Setting The VR provides differential remote sense inputs to eliminate the effects of voltage drops along the PC board traces CPU internal power routes and socket contacts The CPU contains on die sense pins VCC_SENSE and VSS_SENSE Connecting RGND to VSS_SENSE and FB to VCC_...

Page 40: ...he ISENxN voltages during start up Normally the VR operates as a 4 phase PWM controller Pulling ISEN4N to VCC programs a 3 phase operation pulling ISEN3Nand ISEN4Nto VCC programs a 2 phase operation and pulling ISEN2N ISEN3N and ISEN4N to VCC programs a 1 phase operation Before POR VR detects whether the voltages of ISEN2N ISEN3N and ISEN4N are higher than VCC 1V respectively to decide how many ph...

Page 41: ...constant matches inductor time constant LX DCRX an expected load transient waveform can be designed If RXCX network time constant is larger than inductor time constant LX DCRX VCORE waveform has a sluggish droop during load transient If RXCX network is smaller than inductor time constant LX DCRX a worst VCORE waveform will sag to create an undershoot to fail the specification Figure 24 shows the v...

Page 42: ...680 DCR T i R T 1 6 680 Where 1 The relationship between DCR and temperature is as follows 2 REQ T is the equivalent resistor of the resistor network with a NTC thermistor DCR T DCR 25 C 1 0 00393 T 25 EQ IMON1 IMON2 IMON3 NTC R T R R R R T And the relationship between NTC and temperature is as follows 1 1 β T 273 298 NTC NTC R T R 25 C e β is in the NTC thermistor datasheet Step3 Three equations ...

Page 43: ...expected load transient waveform RxCx time constant needs to match Lx DCRx per phase Cx 1μF is set then F Ω μ X X X L R 500 1 DCR IMON resistor network design TL 25 C TR 50 C and TH 100 C are decided NTC thermistor 100kΩ 25 C β 4485 and ICCMAX 90A According to the sub section Current Loop Design in Details RIMON1 5 43kΩ RIMON2 12 6kΩ and RIMON3 13 9kΩ can be decided The REQ 25 C 16 8kΩ Load line d...

Page 44: ...n depends on the thermal resistance of the IC package PCB layout rate of surrounding airflow and difference between junction and ambient temperature The maximum power dissipation can be calculated by the following formula PD MAX TJ MAX TA θJA where TJ MAX is the maximum junction temperature TA is the ambient temperature and θJA is the junction to ambient thermal resistance For recommended operatin...

Page 45: ... the ground terminals Keep the power traces and load connections short This is essential for high efficiency When trade offs in trace lengths must be made it s preferable to let the inductor charging path be longer than the discharging path Place the current sense component close to the controller ISENxP and ISENxNconnections for current limit and voltage positioning must be made using Kelvin sens...

Page 46: ...e accurate and reliable However no responsibility is assumed by Richtek or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max M...

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