RSK+RZA1H
5. QSPI Boot Loader
R20UT2845EG0200
Rev.
2.00
Page 27 of 34
5. QSPI Boot Loader
5.1
Loading Process
When the configuration switch SW6 is set to OFF, ON, OFF, ON, ON, ON, the RZ/A1H processor configures
the QSPI bus controller in external address space read mode to boot and execute from location 0x1800000
(QSPI channel 0 bus area). It sets the QSPI in single device, one bit mode at the lowest speed. The boot
loader is only located in the first device (IC26) connected to QSPI channel 0’s Port 0. The following actions
takes place:
The boot loader will transfer a small section (section 1: Spibsc_init1) of the code into RAM and
execute it. This code will speed up the QSPI access before returning back to boot loader code, as the
speed cannot be altered whilst the code is running from QSPI.
The boot loader then transfers the next section (section 2: Spibsc_init2) of the code into RAM and
executes it. This code will change the QSPI mode of operation to dual QSPI in quad mode, enabling
data transfer of 8 bits at a time. It then checks if a user application is present in the QSPI starting from
location 0x18080000. The check is performed by reading a signature at offset 0x2C.
Offset 0x20 contains the start address of the code, offset 0x24 contains the end address, and 0x28
contains the execution start address.
It uses the above information to determine if the code has to be transferred into RAM (if the start
address is in RAM), or execute in QSPI.
It transfers the code if necessary and then jumps to the execution start address.
Transfer of QSPI device data to the RZ/A1H On-chip RAM
The QSPI Flash device is shown mapped to the RZ/A1H’s QSPI bus area.
Mar 21, 2014
Summary of Contents for RZ/A1H Series
Page 34: ...RZA1H Group R20UT2845EG0200 ...
