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Renesas RYZ012 User Manual Download Page 149

RYZ012 

Multi-Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802.15.4 

R15UH0002EU0103  Rev.1.03 

 

Page 149 of 206 

Apr.21.21 

 

Figure 26. SDM Block Diagram 

 

12.4.3

 

Register Configuration 

Bit  1  to  4  of 

AUDIO_OUT:CTRL

  should  be  set  to  1b'1  to  enable  I2S  recorder,  ISO  player,  SDM  player  and  I2S  player,  while 

AUDIO_OUT:CTRL:MODE

 is to select either mono or stereo audio output. 

AUDIO_OUT:CTRL:HPFEN

 should be set to 1b'1 to enable the 

HPF in audio output path. 

AUDIO_OUT:VOL_CTRL

 controls the volume level. 

AUDIO_OUT:PWM_CTRL:IPSEL

  serves  to  select  either  linear  interpolation  or  delay  interpolation  for  the  rate  matching  block.  Setting 

AUDIO_OUT:PWM_CTRL:IPSEL

 to 0b'1 is to select linear interpolation, while clearing the bit is to select delay interpolation. 

Input for SDM Dither control is configurable through 

AUDIO_OUT:PN_CTRL

 and 

AUDIO_OUT:PWM_CTRL

. 

For the left channel:   

 

AUDIO_OUT:PN_CTRL:PNLEN

 should be set to 1b'1 to select a constant DC input. When DC input is used, 

AUDIO_OUT:CONST_LEFT

 serves to configure the input constant value.  

 

AUDIO_OUT:PN_CTRL:PNLEN

 should be set to 1b'0 to use the PN generator. 

AUDIO_OUT:PWM_CTRL:LSEN

 serves to enable/mask 

the dither shaping module. There are two PN generators to generate random dithering sequence. 

AUDIO_OUT:PN_CTRL:PN2LEN

 or 

AUDIO_OUT:PN_CTRL:PN1LEN

 enable the corresponding PN generator.  

1.  To select the PN sequence as input, 

AUDIO_OUT:PN_CTRL:PNLEN

 and 

AUDIO_OUT:PWM_CTRL:LSEN

 should be set to 1b'0 and 

AUDIO_OUT:PN_CTRL:PN2LEN

 and 

AUDIO_OUT:PN_CTRL:PN1LEN

 should be set to 1b'1.  

2.  To select the PN sequence with Shaping as input, 

AUDIO_OUT:PN_CTRL:PNLEN

 should be set to 1b'0 and 

AUDIO_OUT:PWM_CTRL:LSEN

, 

AUDIO_OUT:PN_CTRL:PN2LEN

 and 

AUDIO_OUT:PN_CTRL:PN1LEN

 should be set to 1b'1.  

 

When PN sequence or PN with Shaping is used, 

AUDIO_OUT:PN_CTRL:BPN1L

 and 

AUDIO_OUT:PN_CTRL:BPN2L

 determines the 

number of bits (ranging from 0 to 16) used in PN1/PN2 generator.  

For the right channel:   

 

AUDIO_OUT:PN_CTRL:PNREN

 should be set to 1b'1 to select constant DC input. When DC input is enabled, 

AUDIO_OUT:CONST_RIGHT

 serves to configure the input constant value.  

 

AUDIO_OUT:PN_CTRL:PNREN

 should be set to 1b'0 to use PN generator. 

AUDIO_OUT:PWM_CTRL:RSEN

 serves to enable/mask the 

dither shaping module. There are two PN generators to generate random dithering sequence. 

AUDIO_OUT:PN_CTRL:PN2REN

 and 

AUDIO_OUT:PN_CTRL:PN1REN

 enable the corresponding PN generator.  

1.  To select the PN sequence as input, 

AUDIO_OUT:PN_CTRL:PNREN

 and 

AUDIO_OUT:PWM_CTRL:RSEN

 should be set to 1b'0, 

AUDIO_OUT:PN_CTRL:PN2REN

 and 

AUDIO_OUT:PN_CTRL:PN1REN

 should be set to 1b'1.  

2.  To select the PN sequence with Shaping as input, 

AUDIO_OUT:PN_CTRL:PNREN

 should be set to 1b'0, 

AUDIO_OUT:PWM_CTRL:RSEN

, 

AUDIO_OUT:PN_CTRL:PN2REN

 and 

AUDIO_OUT:PN_CTRL:PN1REN

 should be set to 1b'1.  

 

When PN sequence or PN with Shaping is used, 

AUDIO_OUT:PN_CTRL:BPN1R

 and 

AUDIO_OUT:PN_CTRL:BPN2R

 determine the 

number of bits (ranging from 0 to 16) used in PN1/PN2 generator. 

The  bits 

AUDIO_OUT:I2SCLK:BSL

  and 

AUDIO_OUT:ASCL_STEP:BSH

  are  to  set  BS  for  the  rate  matching  block,  while 

AUDIO_OUT:ASCL_TUNE:TBS

 is to tune the BS value. BS should be in accordance with the F

I2S

 provided by the SDM/I2S clock. 

Summary of Contents for RYZ012

Page 1: ...ication up to Bluetooth 5 and allows simple connectivity with Bluetooth Low Energy mobile phones tablets and laptops The Bluetooth Low Energy stack supports Bluetooth Low Energy slave and master mode operation including broadcast encryption connection updates and channel map updates Combining Bluetooth Low Energy with IEEE 802 15 4 based standards such as ZigBee or Thread creates an interoperable ...

Page 2: ...a single SoC including Bluetooth Low Energy Bluetooth Low Energy Mesh ZigBee RF4CE HomeKit 6LowPAN Thread ANT and 2 4GHz proprietary technologies without the requirement for an external DSP RF Features Bluetooth Low Energy 802 15 4 2 4GHz RF transceiver embedded working in worldwide 2 4GHz ISM band Bluetooth 5 Compliant 1Mbps 2Mbps Long Range 125kbps and 500kbps IEEE802 15 4 compliant 250kbps 2 4G...

Page 3: ...uetooth 5 support Long range support with 125Kbps and 500Kbps data rate Bluetooth Mesh support Renesas proprietary Mesh support Bluetooth Low Energy location and up to 8 antenna indoor positioning support Renesas extended profile with audio support for voice command based searches Bluetooth Mesh Features Compatible with Bluetooth Mesh specification 1 0 with additional features from Renesas enhance...

Page 4: ...2 3 System Control 23 3 1 Reset 23 3 2 Power Supply 23 3 2 1 Power On Reset POR and Brown out Detect 23 3 3 Power Management 26 3 3 1 Active Mode 26 3 3 2 Idle Mode 26 3 3 3 Suspend Mode 26 3 3 4 Deep Sleep Mode 26 3 3 5 Standby Mode 27 3 3 6 Shutdown Mode 27 3 3 7 Wakeup Sources 27 3 3 8 Retention Registers 27 3 4 Clock 28 3 4 1 System Clock 28 3 4 2 Peripheral Clocks 29 3 5 Register Reference 29...

Page 5: ...Data 4 41 3 6 10 SCTL RD5 Retention Data 5 41 3 6 11 SCTL RD6 Retention Data 6 42 3 6 12 SCTL RD7 Retention Data 7 42 3 6 13 SCTL SSTATUS System Status 42 3 6 14 SCTL APCTRL Analog Power Control 43 4 Interrupt System 44 4 1 Register Reference 45 4 1 1 IRQ MASK Interrupt Mask Configuration 45 4 1 2 IRQ GIEN Global Interrupt Enable 46 4 1 3 IRQ PRIO Interrupt Priority Configuration 47 4 1 4 IRQ IPS ...

Page 6: ...FS Peripheral Function Selection Register 62 5 5 10 GPIOB T0G2R GPIOB Extra Peripheral Mapping 0 63 5 5 11 GPIOB T1G2R GPIOB Extra Peripheral Mapping 1 63 5 5 12 GPIOB T2 GPIOB Extra Peripheral Mapping 2 63 5 6 GPIOB Analog Register Reference 64 5 6 1 GPIOB PRC Port B Pull Resistor Control Low 64 5 6 2 GPIOB WKUPPOL GPIOB Wakeup Polarity Control 64 5 6 3 GPIOB WKUPEN GPIOB Wakeup Enable 64 5 7 GPI...

Page 7: ...pping 1 75 5 9 12 GPIOD T2 GPIOD Extra Peripheral Mapping 2 75 5 10 GPIOD Analog Register Reference 76 5 10 1 GPIOD PRC Port D Pull Register Control Low 76 5 10 2 GPIOD WKUPPOL GPIOD Wakeup Polarity Control 76 5 10 3 GPIOD WKUPEN GPIOD Wakeup Enable 76 6 I2C Interface 77 6 1 Communication Protocol 77 6 2 I2C Slave Mode 77 6 2 1 DMA Mode 77 6 2 2 Mapping Mode 78 6 3 Master Mode 79 6 3 1 Write Trans...

Page 8: ...unt 93 8 1 6 UART STATUS UART Status 94 8 1 7 UART TXRX_STATUS UART RX TX Status 94 8 1 8 UART STATE UART State 95 9 Single Wire Interface 95 10 Timers 95 10 1 General Purpose Timers Timer 0 Timer 2 95 10 1 1 Mode 0 System Clock Mode 95 10 1 2 Mode 1 GPIO Trigger Mode 96 10 1 3 Mode 2 GPIO Pulse Width Mode 96 10 1 4 Mode 3 Tick Mode 96 10 1 5 Watchdog 97 10 2 32K LTIMER 97 10 3 Register Reference ...

Page 9: ...M2 Capture Mode Time 110 11 2 12 PWM TMAX2 PWM2 Maximum Cycle Time 110 11 2 13 PWM TCMP3 PWM3 Capture Mode Time 110 11 2 14 PWM TMAX3 PWM3 Maximum Cycle Time 111 11 2 15 PWM TCMP4 PWM4 Capture Mode Time 111 11 2 16 PWM TMAX4 PWM4 Maximum Cycle Time 111 11 2 17 PWM TCMP5 PWM5 Capture Mode Time 112 11 2 18 PWM TMAX5 PWM5 Maximum Cycle Time 112 11 2 19 PWM PNUM0 PWM0 Pulse Number 112 11 2 20 PWM MASK...

Page 10: ...FIFO0 Depth 125 12 3 4 AUDIO_IN DFIFO0_BADR2 DFIFO0 Base Address 125 12 3 5 AUDIO_IN DFIFO1_BADR0 DFIFO1 Base Address 126 12 3 6 AUDIO_IN DFIFO1_BADR1 DFIFO1 Base Address 126 12 3 7 AUDIO_IN DFIFO1_DEPTH DFIFO1 Depth 126 12 3 8 AUDIO_IN DFIFO1_BADR2 DFIFO1 Base Address 126 12 3 9 AUDIO_IN DFIFO2_BADR0 DFIFO2 Base Address 127 12 3 10 AUDIO_IN DFIFO2_BADR1 DFIFO2 Base Address 127 12 3 11 AUDIO_IN DF...

Page 11: ...IO_IN ALC_VOL_R ALC Right Channel Setting 139 12 3 41 AUDIO_IN ALC_VOL_H Maximum PGA Gain Limit 139 12 3 42 AUDIO_IN ALC_VOL_THH PGA High Volume Target 140 12 3 43 AUDIO_IN ALC_VOL_THL PGA LOW volume Target 140 12 3 44 AUDIO_IN ALC_VOL_THN PGA Noise Level Target 140 12 3 45 AUDIO_IN ALC_VOL_L_R PGA Left Channel Gain 141 12 3 46 AUDIO_IN ALC_VOL_R_R PGA Right Channel Gain 141 12 3 47 AUDIO_IN ALC_P...

Page 12: ...RL Audio Out PWM Control 151 12 5 5 AUDIO_OUT ASCL_TUNE Tune Step 152 12 5 6 AUDIO_OUT I2SCLK I2S Clock configuration 152 12 5 7 AUDIO_OUT ASCL_STEP Rate Matching Block Step 153 12 5 8 AUDIO_OUT PN_CTRL PN Generator Control 153 12 5 9 AUDIO_OUT CONST_LEFT Constant Left Channel 154 12 5 10 AUDIO_OUT CONST_RIGHT Constant Right Channel 155 13 Quadrature Decoder 156 13 1 Input Pin Selection 156 13 2 C...

Page 13: ...le Control 174 14 2 9 SAR_ADC CLKDIV SAR Clock Divider Configuration 175 14 2 10 SAR_ADC DATM SAR Data Misc Channel 175 14 2 11 SAR_ADC APSC Analog Pre scaler 175 15 Programmable Gain Amplifier PGA 176 15 1 Power on down 176 15 2 Input Channel 176 15 3 Adjust Gain 177 15 4 Analog Register Reference 177 15 4 1 PGA VINSEL PGA Channel Input Configuration 177 16 Temperature Sensor 179 17 Low Power Com...

Page 14: ...nformation 206 24 Marking Diagram 206 25 Revision History 206 List of Figures Figure 1 Pin Assignments Top View 17 Figure 2 Reading and Writing Analog Registers 21 Figure 3 Power Control Logic 23 Figure 4 Power Up Sequence 24 Figure 5 Power Down Sequence 25 Figure 6 Wakeup Logic 27 Figure 7 Clock Tree 28 Figure 8 Schematic of a GPIO bit 50 Figure 9 GPIO Signal Forwarding to Timers and Interrupt Sy...

Page 15: ...ure 37 Recommended Soldering Profile 205 List of Tables Table 1 Pin Descriptions 17 Table 2 Register File 18 Table 3 Physical Memory Map 19 Table 4 Flash Memory Partition 20 Table 5 E Fuse Information 20 Table 6 Characteristics of the Power Control Logic 25 Table 7 Power Saving Modes Overview 26 Table 8 List of interrupts 44 Table 9 GPIO Configuration Register Overview 50 Table 10 Peripheral Funct...

Page 16: ...tics VDD 3 3V TA 25 C 190 Table 25 Bluetooth Low Energy 1 Mbps Mode 191 Table 26 Bluetooth Low Energy 2 Mbps Mode 191 Table 27 Bluetooth Low Energy 500 kbps Mode 192 Table 28 Bluetooth Low Energy 125 kbps Mode 193 Table 29 IEEE 802 15 4 250kbps 194 Table 30 SPI Characteristics over process voltage 1 9 3 6V and TA 40 to 85 C 195 Table 31 I2C Characteristics over process voltage 1 9 3 6V and TA 40 t...

Page 17: ...WS enabled after power on 4 PB1 Digital I O 8 mA 4 mA UART TX 5 PB4 Digital I O 16 mA 12 mA Interrupt 6 PB5 Digital I O 16 mA 12 mA UART SPI Select Set low for UART set high for SPI 7 PB6 Digital I O 16 mA 12 mA SPI DI 8 PB7 Digital I O 16 mA 12 mA SPI DO 9 VDD Supply N A Power supply input 10 PC0 Digital I O 4 mA 2 mA UART RTS 11 PC1 Digital I O 4 mA 2 mA Unused 12 PC4 Digital I O 4 mA 2 mA UART ...

Page 18: ...ister SP holds the current value of the call stack It is decremented automatically when data is pushed to the stack and incremented when data is popped As the MCU has two stacks for normal operation and interrupt servicing the register file has two stack pointers The stack that is active depends on the operating mode The Program Counter PC and Link Register LR are used to control the program flow ...

Page 19: ...ODEM 0x801200 LINK LAYER 0x800F00 256 DMA 0x800c00 256 DMA FIFO 0x800b00 256 PWM 0x800780 128 SYS_TIMER 0x800740 46 TIMER 0x800620 224 MCU 0x800600 32 GPIO 0x800580 128 AUDIO 0x800560 32 AES 0x800540 32 BASEBAND 0x800400 256 I2C address map 0x8000E0 32 QDEC 0x8000D0 16 UART 0x8000B4 4 SWIRE 0x8000B0 4 UART 0x800090 16 SCTL 0x800040 64 SPI 0x800008 4 I2C 0x800000 8 Flash Space Flash Memory 0x000000...

Page 20: ...an encrypt the UID read from the chip flash through AES generating a unique cipher text that is written into the E Fuse section During application startup an encryption authentication procedure is added The user should use the same key and AES encryption algorithm and key to encrypt the UID read from the chip flash and generate new cipher text Before running the main application firmware the new c...

Page 21: ...pped starting from address 0x800000 Similar to the SRAM they are accessed by reading and writing the corresponding address For convenience the SDK defines usable mnemonics Peripheral registers in the analog domain are not directly accessible These registers need to be accessed indirectly through ARA CTRL ARA ADDR and ARA DATA The figure below shows the register read and write procedures Figure 2 R...

Page 22: ... Register Data Address 0x00b9 Reset 0x00 7 6 5 4 3 2 1 0 ARA DATA DATA rw 0 7 0 DATA Input Output data 2 3 3 ARA CTRL Access Control Address 0x00ba Reset 0x00 7 6 5 4 3 2 1 0 ARA CTRL RSVD CYC RDWR CONT RSVD BSY rw 0 rw 0 rw 0 rw 0 rw 0 r 0 6 CYC ToDo 5 RDWR Read write control 0 Read register 1 Write register 4 CONT Continuous access read mode 0 Single read operation 1 Automatically start new read...

Page 23: ...operation The chip embedded DCDC generates 1 8V output voltage as power supply for the internal flash and generates 1 4V output voltage as input to the LDO The embedded LDO regulator takes the 1 4V voltage output from the DCDC and generates 1 2V regulated voltage to supply power for 1 2V digital core and analog modules 3 2 1 Power On Reset POR and Brown out Detect The modules power supply status i...

Page 24: ...RYZ012 Multi Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 24 of 206 Apr 21 21 Figure 4 Power Up Sequence ...

Page 25: ... Apr 21 21 Figure 5 Power Down Sequence Table 6 Characteristics of the Power Control Logic Symbol Parameter Minimum Typical Maximum Unit VPOR VDD voltage when VUVLO turns to high level 1 62 V VPDN VDD voltage when VUVLO turns to low level 1 55 V TDLY Delay counter value Configurable through register SCTL PON_DLY 16kHz clock cycles ...

Page 26: ...uspend 1ms 10ms Current Table 23 DC Electrical Characteristics 3 3 1 Active Mode In Active mode MCU is active all SRAMs are accessible and other modules are selectable whether to be at working state 3 3 2 Idle Mode The chip can switch to Idle mode to stall the MCU In this mode all SRAMs are still accessible modules such as RF transceiver and Audio continue working if they had been enabled before T...

Page 27: ...ipheral units or by reset which is triggered by the NRST pin GPIO wakeup can be supported if the GPIO interrupt functionality is used Wakeup from Suspend Deep Sleep and Standby mode is done through a wakeup logic as illustrated below GPIO wakeup 32kHz Timer and Low Power Comparator wakeup can be enabled individually through bits in register SCTL WKUPEN After wakeup the lower four bits of register ...

Page 28: ...change this to a suitable configuration The figure below gives an overview of the clock tree and shows the registers that are required to change the configuration of the clock tree Most peripheral clocks are gated through register SCTL PCEN by default The application firmware must enable the clocks of the peripheral units that are used by the application Figure 7 Clock Tree 3 4 1 System Clock The ...

Page 29: ...2 3 DMIC Clock Bit SCTL DMICC CEN enables the DMIC clock output For normal DMIC operation SCTL LSC DMICS should be set to 0b1 to select the clock derived from the 48MHz clock The clock speed is configured as FDMIC 48MHz SCTL DMICC STEP SCTL DMIC_MOD SCTL DMIC_MOD must not be less than 2 SCTL DMICC STEP If the DMIC Clock is not required but a clock for the 32kHz timer is required SCTL LSC DMICS sho...

Page 30: ...in reset state 17 AUDIO Audio Reset 0 Module operating normally 1 Module is held in reset state 16 AIF AIF reset 0 Module operating normally 1 Module is held in reset state 14 ALG ALG reset 0 Module operating normally 1 Module is held in reset state 13 ADC ADC reset 0 Module operating normally 1 Module is held in reset state 12 AES AES reset 0 Module operating normally 1 Module is held in reset st...

Page 31: ...ART reset 0 Module operating normally 1 Module is held in reset state 1 I2C I2C reset 0 Module operating normally 1 Module is held in reset state 0 SPI SPI reset 0 Module operating normally 1 Module is held in reset state 3 5 2 SCTL PCEN Peripheral Clock Enable 1 Address 0x0063 Reset 0x300083 7 6 5 4 3 2 1 0 SCTL PCEN 2 RSVD MCICEN RISCEN DMAEN DFIFOEN AUDIOEN AIFEN rw 0 rw 1 rw 1 rw 0 rw 0 rw 0 r...

Page 32: ...e clock 16 AIFEN AIF clock enable control 0 Disables module clock 1 Enables module clock 12 AESEN AES clock enable control 0 Disables module clock 1 Enables module clock 11 ALGMEN ALGM clock enable control 0 Disables module clock 1 Enables module clock 9 SYSTIMEN System Timer clock enable control 0 Disables module clock 1 Enables module clock 8 BBEN BB clock enable control 0 Disables module clock ...

Page 33: ...control 0 Disables module clock 1 Enables module clock 3 5 3 SCTL HSC1 System Clock Configuration Address 0x0066 Reset 0x06 7 6 5 4 3 2 1 0 SCTL HSC1 HS0S SCS SCD rw 0 rw 0 rw 6 7 HS0S HS0 clock selection 0 Selects 48M clock 1 Selects RC24 clock 6 5 SCS System clock selection 00 RC24 clock selected as System Clock source 01 HS1 clock selected as System Clock source 10 HS1 SCS selected as System Cl...

Page 34: ... clock 0 Disables I2S clock 1 Enables I2S clock 6 0 STEP I2S step 3 5 5 SCTL I2S_MOD I2S Clock Modifier Address 0x0068 Reset 0x02 7 6 5 4 3 2 1 0 SCTL I2S_MOD I2S_MOD rw 2 7 0 I2S_MOD FI2S 48M I2SCC STEP I2S_MOD I2S_MOD should be larger than or equal to 2 I2SCC STEP 3 5 6 SCTL DMICC DCMI Clock Control Address 0x006c Reset 0x01 7 6 5 4 3 2 1 0 SCTL DMICC CEN STEP rw 0 rw 1 7 CEN Enable Digital MIC ...

Page 35: ...2CSYNEN GPIOEN RSVD SPIEN I2CEN rw 0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 7 SLEEPEN Enable sleep wakeup resume reset system 0 Disables sleep wakeup 1 Enables sleep wakeup 5 RGPIOEN Enable GPIO remote wakeup resume 0 Disables remote GPIO wakeup 1 Enables remote GPIO wakeup 4 I2CSYNEN Enable I2C synchronous interface wakeup 0 Disables wakeup from I2C synchronous interface 1 Enables wakeup from I2C syn...

Page 36: ...ger 0 No action 1 Trigger low power mode entry If bit SUSP is set system will enter Suspend Mode If bit SUSP is cleared the MCU will be stalled 5 SRST Reset all act as watchdog reset 0 No action 1 Resets the whole chip similar to watchdog reset 0 SUSP Suspend Mode control 0 Disables suspend mode 1 Enables suspend mode 3 5 10 SCTL HSC2 HS1 Clock Configuration Address 0x0070 Reset 0x00 7 6 5 4 3 2 1...

Page 37: ... rw 0 rw 0 0 STATE Watch dog status indication 0 No Watchdog indication detected 1 Watchdog indication detected Write 1 to clear 3 5 12 SCTL LSC Oscillator Clock Configuration Address 0x0073 Reset 0x04 7 6 5 4 3 2 1 0 SCTL LSC RSVD DMICS LSS rw 1 w 0 rw 0 1 DMICS DMIC clock select 0 Select DMIC clock divider 1 Select 32kHz oscillator 0 LSS Low speed clock select 0 Select RC_32k from RC oscillator ...

Page 38: ...ower up module 1 Power down module 6 BUSLDOPD Power control of VBUS_LDO 0 Power up module 1 Power down module 5 DCDCPD Power control of DCDC 0 Power up module 1 Power down module 4 PLPD Power control of power logic 4 2V VBUS_LDO and DCDC 0 Power up module 1 Power down module 3 X24MPD Power control of 24MHz crystal oscillator 0 Power up module 1 Power down module 2 RC24MPD Power control of 24MHz RC...

Page 39: ... of temperature sensor 0 Power up module 1 Power down module 3 LPCPD Power control of LPC 0 Power up module 1 Power down module 2 RDPD Power control of retention LDO 0 Power up module 1 Power down module 1 DLDOPD Power control of main digital LDO 0 Power up module 1 Power down module 0 SPDLDO Power control of SPD LDO 0 Power up module 1 Power down module 3 6 3 SCTL PON_DLY Power on delay Address 0...

Page 40: ...p source 6 TIM32EN 32kHz timer wakeup control 0 Disables module as wakeup source 1 Enables module as wakeup source 4 GPIOEN GPIO wake up control 0 Disables module as wakeup source 1 Enables module as wakeup source 3 IOFILT GPIO wakeup filter control 0 Combinational logic output disable filter 1 Select 16μs filter to filter out jitter on IO PAD input 3 6 5 SCTL RD0 Retention Data 0 Address 0x0035 R...

Page 41: ... 6 8 SCTL RD3 Retention Data 3 Address 0x0038 Reset 0x00 7 6 5 4 3 2 1 0 SCTL RD3 RD3 rw 0 7 0 RD3 Application data buffer 3 6 9 SCTL RD4 Retention Data 4 Address 0x0039 Reset 0xff 7 6 5 4 3 2 1 0 SCTL RD4 RD4 rw 255 7 0 RD4 Application data buffer 3 6 10 SCTL RD5 Retention Data 5 Address 0x003a Reset 0x00 7 6 5 4 3 2 1 0 SCTL RD5 RD5 rw 0 7 0 RD5 Application data buffer Note This field is only re...

Page 42: ...6 5 4 3 2 1 0 SCTL RD7 RD7 rw 0 7 0 RD7 Application data buffer Note This field is only reset by power on reset Data is retained after Watchdog or System Reset 3 6 13 SCTL SSTATUS System Status Address 0x0044 Reset 0x00 7 6 5 4 3 2 1 0 SCTL SSTATUS DCDC_RDY WD_STATE CAL_24M CAL_32K IO_WKUP RSVD T32_WKUP LPC_WKUP r 0 rw1c 0 r 0 r 0 rw1c 0 r 0 rw1c 0 rw1c 0 7 DCDC_RDY DCDC converter status 0 DCDC is...

Page 43: ...last wakeup event was triggered from 32kHz timer Write 1 to clear 0 LPC_WKUP Set to 1 if last wakeup event was triggered from LPC Write 1 to clear 3 6 14 SCTL APCTRL Analog Power Control Address 0x00fc Reset 0xE0 7 6 5 4 3 2 1 0 SCTL APCTRL PGAR PGAL ADC RSVD rw 1 rw 1 rw 1 rw 0 7 PGAR PGA right channel power control low active 0 Enable module power 1 Disable module power 6 PGAL PGA left channel p...

Page 44: ...f each interrupt is configurable through register IRQ PRIO to be at one of two possible levels high priority or low priority High priority interrupts can interrupt low priority ISRs Table 8 List of interrupts Nr Unit Description Level triggered interrupts 0 TIM0 Timer 0 interrupt 1 TIM1 Timer 1 interrupt 2 TIM2 Timer 2 interrupt 4 DMA DMA interrupt 5 DFIFO DFIFO interrupt 6 UART UART interrupt 7 I...

Page 45: ...RISC0 level triggered interrupt 1 Activate GPIO to RISC0 level triggered interrupt 20 SYSTIM Configure System Timer interrupt enable mask bit 0 Deactivate System Timer level triggered interrupt 1 Activate System Timer level triggered interrupt 19 LSTIM Configure PMTM interrupt enable mask bit 0 Deactivate PMTM level triggered interrupt 1 Activate PMTM level triggered interrupt 18 GPIO Configure GI...

Page 46: ...ivate DMA level triggered interrupt 2 TIM2 Configure Timer 2 interrupt enable mask bit 0 Deactivate Timer 2 level triggered interrupt 1 Activate Timer 2 level triggered interrupt 1 TIM1 Configure Timer 1 interrupt enable mask bit 0 Deactivate Timer 1 level triggered interrupt 1 Activate Timer 1 level triggered interrupt 0 TIM0 Configure Timer 0 interrupt enable mask bit 0 Deactivate Timer 0 level ...

Page 47: ...t 0 Set LOW priority interrupt to specified module 1 Set HIGH priority interrupt to specified module 19 LSTIM Configure PMTM interrupt priority configuration bit 0 Set LOW priority interrupt to specified module 1 Set HIGH priority interrupt to specified module 18 GPIO Configure GIPO interrupt priority configuration bit 0 Set LOW priority interrupt to specified module 1 Set HIGH priority interrupt ...

Page 48: ...t HIGH priority interrupt to specified module 0 TIM0 Configure Timer 0 interrupt priority configuration bit 0 Set LOW priority interrupt to specified module 1 Set HIGH priority interrupt to specified module 4 1 4 IRQ IPS Interrupt Pending Status Address 0x0648 Reset 0x000000 7 6 5 4 3 2 1 0 IRQ IPS 2 RSVD G2R1 G2R0 SYSTIM LSTIM GPIO RSVD r 0 rw1 0 rw1 0 rw1 0 rw1 0 rw1 0 r 0 IRQ IPS 1 RSVD PWM BB ...

Page 49: ... is NO triggered interrupt on specified module 1 There is A triggered interrupt on the specified module 6 UART Read UART interrupt trigger state 0 There is NO triggered interrupt on specified module 1 There is A triggered interrupt on the specified module 5 DFIFO Read DFIFO interrupt trigger state 0 There is NO triggered interrupt on specified module 1 There is A triggered interrupt on the specifi...

Page 50: ...put disable Set to 1 to disable the output driver A B C D OD Output data register Values written to this registers are driven on the output if corresponding ODIS register is cleared A B C D DS Driving strength control A value of 0b1 selects high driving strength See Table 1 for absolute values A B C D MODE GPIO or peripheral mode select If bit is set to 0b1 GPIO mode is selected otherwise one of t...

Page 51: ...elow For both timer input and interrupt input the incoming GPIO signal is XOR ed with GPIOx INTPOL to control the phase that is used to trigger the timer action or interrupt The registers GPIOx INTEN GPIOx T0G2R GPIOx T1G2R and GPIOx T2 control to which units the GPIO signal is forwarded Figure 9 GPIO Signal Forwarding to Timers and Interrupt System 5 2 GPIO Peripheral Multiplexing Table 10 shows ...

Page 52: ... 1 7 1 4 5 6 7 0 1 2 3 4 2 3 4 7 Pin Nr 2 3 4 5 9 10 11 12 15 16 17 18 19 22 23 24 1 UART RX 2 2 1 TX 1 RTS 1 2 2 CTS 1 7816 TRX 1 2 2 CLK 1 SPI DI 1 DO 1 CK 0 CN 0 DMIC DI 0 CLK 0 I2S SDI 1 SDO 1 LR 1 CLK 2 BCLK 1 I2C SCK 0 2 SDA 0 2 PWM0 1 N 2 0 2 N PWM1 1 N 0 0 N PWM2 0 2 N PWM3 2 PWM4 0 1 1 N PWM5 1 SDM 0 P0 0 N0 0 P1 0 N1 Analog ADC 1 4 5 6 7 8 LPC 1 4 5 6 7 PGA 0P 0N 1P 1N SWIRE SWS 0 SWM 0 ...

Page 53: ... signal level is indicated bitwise for the corresponding pin 0 Digital LOW level signal is available at the corresponding pin 1 Digital HIGH level signal is available at the corresponding pin 5 3 2 GPIOA IEN GPIOA Input Enable For all unused GPIOs the corresponding IEx must be disabled Address 0x0581 Reset 0x00 7 6 5 4 3 2 1 0 GPIOA IEN IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 54: ...OD GPIOA Output Data Address 0x0583 Reset 0x00 7 6 5 4 3 2 1 0 GPIOA OD CFGO7 CFGO6 CFGO5 CFGO4 CFGO3 CFGO2 CFGO1 CFGO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 CFGOx GPIOA Output Data Set digital output level to corresponding pin 0 Set digital LOW on corresponding pin 1 Set digital HIGH on corresponding pin 5 3 5 GPIOA INTPOL GPIOA Interrupt Polarity Address 0x0584 Reset 0x00 7 6 5...

Page 55: ... 7 6 5 4 3 2 1 0 GPIOA MODE MODE7 MODE6 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 0 1 2 3 4 5 6 7 MODEx GPIOA Mode Selection Controls whether GPIO or peripheral mode is used for the corresponding bit 0 Pin is controlled by peripheral selected through PFS register 1 Pin is used as general purpose I O 5 3 8 GPIOA INTEN GPIOA Interrupt Enable Address 0x0587 Reset 0x0...

Page 56: ...elect if pin is configured in peripheral mode 00 DMIC_CLK 01 7816_CLK 10 I2S_CLK 1 0 PF0 Peripheral select if pin is configured in peripheral mode 00 DMIC_DI 01 PWM0_N 10 UART_RX 5 3 10 GPIOA T0G2R GPIOA Extra Peripheral Mapping 0 Address 0x05b8 Reset 0x00 7 6 5 4 3 2 1 0 GPIOA T0G2R T0G2R7 T0G2R6 T0G2R5 T0G2R4 T0G2R3 T0G2R2 T0G2R1 T0G2R0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 T0G...

Page 57: ...eripheral mapping Using this register individual GPIO pins can be mapped to Timer 1 or to the GPIO2RISC IRQ1 interrupt source 0 GPIO is not mapped to Timer 1 and GPIO2RISC IRQ1 1 GPIO is mapped to Timer 1 and GPIO2RISC IRQ1 5 3 12 GPIOA T2 GPIOA Extra Peripheral Mapping 2 Address 0x05c8 Reset 0x00 7 6 5 4 3 2 1 0 GPIOA T2 T2_7 T2_6 T2_5 T2_4 T2_3 T2_2 T2_1 T2_0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 58: ...ll down resistor connected typical 160kΩ 11 Strong pull up resistor connected typical 18kΩ 5 4 2 GPIOA WKUPPOL GPIOA Wakeup Polarity Control Address 0x0021 Reset 0x00 7 6 5 4 3 2 1 0 GPIOA WKUPPOL POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 POLx PA corresponding pin wakeup polarity level selection 0 Select LOW level on Port Pin to trigger wakeup ...

Page 59: ... signal level is indicated bitwise for the corresponding pin 0 Digital LOW level signal is available at the corresponding pin 1 Digital HIGH level signal is available at the corresponding pin 5 5 2 GPIOB IEN GPIOB Input Enable For all unused GPIOs the corresponding IEx must be disabled Address 0x0589 Reset 0x00 7 6 5 4 3 2 1 0 GPIOB IEN IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 60: ...OB Output Data Address 0x058b Reset 0x00 7 6 5 4 3 2 1 0 GPIOB OD CFGO7 CFGO6 CFGO5 CFGO4 CFGO3 CFGO2 CFGO1 CFGO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 CFGOx GPIOB Output Data Set digital output level to corresponding pin 0 Set digital LOW on corresponding pin 1 Set digital HIGH on corresponding pin 5 5 5 GPIOB INTPOL GPIOB Interrupt Polarity Address 0x058c Reset 0x00 7 6 5 4 3 2...

Page 61: ... 6 5 4 3 2 1 0 GPIOB MODE MODE7 MODE6 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 0 1 2 3 4 5 6 7 MODEx GPIOB Mode Selection Controls whether GPIO or peripheral mode is used for the corresponding bit 0 Pin is controlled by peripheral selected through PFS register 1 Pin is used as general purpose I O 5 5 8 GPIOB INTEN GPIO Interrupt Enable PB Address 0x058f Reset 0x0...

Page 62: ...1 RSVD rw 0 rw 0 rw 0 15 14 PF7 Peripheral select if pin is configured in peripheral mode 00 SDM_N1 01 SPI_DO 10 UART_RX 13 12 PF6 Peripheral select if pin is configured in peripheral mode 00 SDM_P1 01 SPI_DI 10 UART_RTS 11 10 PF5 Peripheral select if pin is configured in peripheral mode 00 SDM_N0 01 PWM5 10 Not used 9 8 PF4 Peripheral select if pin is configured in peripheral mode 00 SDM_P0 01 PW...

Page 63: ... GPIOB T1G2R GPIOB Extra Peripheral Mapping 1 Address 0x05c1 Reset 0x00 7 6 5 4 3 2 1 0 GPIOB T1G2R T1G2R7 T1G2R6 T1G2R5 T1G2R4 T1G2R3 T1G2R2 T1G2R1 T1G2R0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 T1G2Rx GPIO extra peripheral mapping Using this register individual GPIO pins can be mapped to Timer 1 or to the GPIO2RISC IRQ1 interrupt source 0 GPIO is not mapped to Timer 1 and GPIO2RI...

Page 64: ...ll down resistor connected typical 160kΩ 11 Strong pull up resistor connected typical 18kΩ 5 6 2 GPIOB WKUPPOL GPIOB Wakeup Polarity Control Address 0x0022 Reset 0x00 7 6 5 4 3 2 1 0 GPIOB WKUPPOL POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 POLx PB corresponding pin wakeup polarity level selection 0 Select LOW level on Port Pin to trigger wakeup ...

Page 65: ... signal level is indicated bitwise for the corresponding pin 0 Digital LOW level signal is available at the corresponding pin 1 Digital HIGH level signal is available at the corresponding pin 5 7 2 GPIOC IEN GPIOC Input Enable For all unused GPIOs the corresponding IEx must be disabled Address 0x0591 Reset 0x00 7 6 5 4 3 2 1 0 GPIOC IEN IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 66: ...OC Output Data Address 0x0593 Reset 0x00 7 6 5 4 3 2 1 0 GPIOC OD CFGO7 CFGO6 CFGO5 CFGO4 CFGO3 CFGO2 CFGO1 CFGO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 CFGOx GPIOC Output Data Set digital output level to corresponding pin 0 Set digital LOW on corresponding pin 1 Set digital HIGH on corresponding pin 5 7 5 GPIOC INTPOL GPIOC Interrupt Polarity Address 0x0594 Reset 0x00 7 6 5 4 3 2...

Page 67: ...7 6 5 4 3 2 1 0 GPIOC MODE MODE7 MODE6 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 0 1 2 3 4 5 6 7 MODEx GPIOC Mode Selection Controls whether GPIO or peripheral mode is used for the corresponding bit 0 Pin is controlled by peripheral selected through PFS register 1 Pin is used as general purpose I O 5 7 8 GPIOC INTEN GPIOC Interrupt Enable PC Address 0x0597 Reset 0...

Page 68: ...rw 1 rw 1 rw 0 rw 0 9 8 PF4 Peripheral select if pin is configured in peripheral mode 00 PWM2 01 UART_CTS 10 PWM0_N 7 6 PF3 Peripheral select if pin is configured in peripheral mode 00 PWM1 01 UART_RX 10 I2C_SCK 5 4 PF2 Peripheral select if pin is configured in peripheral mode 00 PWM0 01 UART_TX 10 I2C_SDA 3 2 PF1 Peripheral select if pin is configured in peripheral mode 00 I2C_SCK 01 PWM1_N 10 PW...

Page 69: ... GPIOC T1G2R GPIOC Extra Peripheral Mapping 1 Address 0x05c2 Reset 0x00 7 6 5 4 3 2 1 0 GPIOC T1G2R T1G2R7 T1G2R6 T1G2R5 T1G2R4 T1G2R3 T1G2R2 T1G2R1 T1G2R0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 T1G2Rx GPIO extra peripheral mapping Using this register individual GPIO pins can be mapped to Timer 1 or to the GPIO2RISC IRQ1 interrupt source 0 GPIO is not mapped to Timer 1 and GPIO2RI...

Page 70: ...ll down resistor connected typical 160kΩ 11 Strong pull up resistor connected typical 18kΩ 5 8 2 GPIOC WKUPPOL GPIOC Wakeup Polarity Control Address 0x0023 Reset 0x00 7 6 5 4 3 2 1 0 GPIOC WKUPPOL POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 POLx PC corresponding pin wakeup polarity level selection 0 Select LOW level on Port Pin to trigger wakeup ...

Page 71: ... signal level is indicated bitwise for the corresponding pin 0 Digital LOW level signal is available at the corresponding pin 1 Digital HIGH level signal is available at the corresponding pin 5 9 2 GPIOD IEN GPIOD Input Enable For all unused GPIOs the corresponding IEx must be disabled Address 0x0599 Reset 0x00 7 6 5 4 3 2 1 0 GPIOD IEN IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 72: ...OD Output Data Address 0x059b Reset 0x00 7 6 5 4 3 2 1 0 GPIOD OD CFGO7 CFGO6 CFGO5 CFGO4 CFGO3 CFGO2 CFGO1 CFGO0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 CFGOx GPIOD Output Data Set digital output level to corresponding pin 0 Set digital LOW on corresponding pin 1 Set digital HIGH on corresponding pin 5 9 5 GPIOD INTPOL GPIOD Interrupt Polarity Address 0x059c Reset 0x00 7 6 5 4 3 2...

Page 73: ...7 6 5 4 3 2 1 0 GPIOD MODE MODE7 MODE6 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 0 1 2 3 4 5 6 7 MODEx GPIOD Mode Selection Controls whether GPIO or peripheral mode is used for the corresponding bit 0 Pin is controlled by peripheral selected through PFS register 1 Pin is used as general purpose I O 5 9 8 GPIOD INTEN GPIOD Interrupt Enable Address 0x059f Reset 0x00...

Page 74: ...ode 00 SWM 01 I2S_SDO 10 PWM2_N 7 6 PF3 Peripheral select if pin is configured in peripheral mode 00 PWM1_N 01 I2S_SDI 10 UART_TX 5 4 PF2 Peripheral select if pin is configured in peripheral mode 00 SPI_CN 01 I2S_LR 10 PWM3 5 9 10 GPIOD T0G2R GPIOD Extra Peripheral Mapping 0 Address 0x05bb Reset 0x00 7 6 5 4 3 2 1 0 GPIOD T0G2R T0G2R7 T0G2R6 T0G2R5 T0G2R4 T0G2R3 T0G2R2 T0G2R1 T0G2R0 rw 0 rw 0 rw 0...

Page 75: ...eripheral mapping Using this register individual GPIO pins can be mapped to Timer 1 or to the GPIO2RISC IRQ1 interrupt source 0 GPIO is not mapped to Timer 1 and GPIO2RISC IRQ1 1 GPIO is mapped to Timer 1 and GPIO2RISC IRQ1 5 9 12 GPIOD T2 GPIOD Extra Peripheral Mapping 2 Address 0x05cb Reset 0x00 7 6 5 4 3 2 1 0 GPIOD T2 T2_7 T2_6 T2_5 T2_4 T2_3 T2_2 T2_1 T2_0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 76: ...ll down resistor connected typical 160kΩ 11 Strong pull up resistor connected typical 18kΩ 5 10 2 GPIOD WKUPPOL GPIOD Wakeup Polarity Control Address 0x0024 Reset 0x00 7 6 5 4 3 2 1 0 GPIOD WKUPPOL POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 6 7 POLx PD corresponding pin wakeup polarity level selection 0 Select LOW level on Port Pin to trigger wakeup...

Page 77: ...d when SCL is low with the exception of the I2C Start and I2C Stop Condition which initiate and terminate a transmission Figure 10 I2C Timing Chart A start condition is always followed by an address byte The I2C master sends the 7 bit ID of the slave followed by a bit that defines whether data is sent to the slave RW 0 or read from the slave RW 1 The slave being addressed needs to acknowledge the ...

Page 78: ... another address sequence The figures below show I2C read and write transfers in DMA Mode for single bytes Figure 11 I2C DMA Mode Read Sequence Figure 12 I2C DMA Mode Write Sequence 6 2 2 Mapping Mode In Mapping mode data I2C data access is limited to a user defined 128 byte buffer in SRAM The buffer start address is configured in register I2C MMADR The lower 64 bytes buffer space is for written d...

Page 79: ...ut the whole transfer without further application interaction The status of the transfer can be monitored in register I2C MST Write transfers with more than 3 bytes can be implemented by leaving out the corresponding stages in I2C CYCTRL 6 3 2 Read Transfer For read transfers in master mode I2C CYCTRL is used similarly to write transfers However the RYZ012 has only one byte receive buffer which is...

Page 80: ...SADR I2C Slave Address Configuration Address 0x0001 Reset 0x5c 7 6 5 4 3 2 1 0 I2C SADR SADR RSVD rw 46 rw 0 7 1 SADR Slave address In master mode this value serves as the remote device slave address In slave mode this value is the address the I2C is accepting requests on 6 5 3 I2C MST I2C Master Status Address 0x0002 Reset 0x00 7 6 5 4 3 2 1 0 I2C MST RSVD ACKSTAT PBSY BSY rw 0 rw 0 rw 0 rw 0 2 A...

Page 81: ...N Clock Stretching Enable 0 Clock is controlled by the master 1 Clock line is held low to suspend the transmission 2 MMEN Mapping Mode enabled 0 Mapping Mode is disabled 1 Mapping Mode is enabled 1 MSTREN I2C Mast Mode enable 0 I2C is operating in Slave Mode 1 I2C is operating in Master Mode 0 AAINC Address Auto Increment enable 0 Address auto increment disabled 1 Address auto increment enabled 6 ...

Page 82: ...ycle Control Address 0x0007 Reset 0x00 7 6 5 4 3 2 1 0 I2C CYCTRL ACKEN RDWR STOPEN STARTEN W3RDEN W2DEN W1DEN ADREN rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 ACKEN Enable ACK in read command 0 Do not acknowledge incoming data 1 Do acknowledge incoming data 6 RDWR Read Write control 0 Send Write Bit 0 after Slave Address 1 Send Read Bit 1 after Slave Address 5 STOPEN Send Stop Condition at the end...

Page 83: ...ot use W1D 1 Send Data from W1D 0 ADREN Enable address transmission from SADR 0 Do not send I2C address byte 1 Send I2C address byte The address is read from I2C SADR the read write bit is taken from RDWR 6 5 9 I2C LHADR I2C Last Hold Address Address 0x00e0 Reset 0x00 7 6 5 4 3 2 1 0 I2C LHADR RSVD ADR r 0 r 0 6 0 ADR Contains the last called data address which is only updated again after I2C STOP...

Page 84: ...I2C Host Status Address 0x00e4 Reset 0x00 7 6 5 4 3 2 1 0 I2C HSTATE RSVD RDY INT rw 0 rw 0 rw 0 1 RDY I2C ready indication 0 The I2C host read operation is NOT complete 1 The I2C host read operation is complete Write 1 to clear 0 INT I2C operation end indication 0 No I2C operation end interrupt detected 1 I2C operation end interrupt detected Write 1 to clear ...

Page 85: ...e rising clock in Slave Mode Figure 15 SPI Timing Diagram 7 1 SPI Master Mode SPI for the RYZ012 supports both master mode and slave mode and acts as slave mode by default To configure Master Mode register SPI CTRL must be set to the appropriate values The bits MSTREN and IOEN must be set to 1 to enable master mode and activate the SPI GPIOs The SPI clock speed is configured in SPI CTRL CPRE The r...

Page 86: ...s following the command byte are used to send or receive data from the RYZ012 SRAM or register space Bit SPI CTRL AAINC determines whether the address received from the master is incremented automatically or not Figure 16 SPI Slave Mode Read and Write Transfers 7 3 Register Reference 7 3 1 SPI DATA SPI Data Address 0x0008 Reset 0x00 7 6 5 4 3 2 1 0 SPI DATA DATA rw 0 7 0 DATA SPI data access 7 3 2...

Page 87: ...tic address incrementing 1 Enables automatic address incrementing 3 RDWR Command direction control 0 Write to DO pin 1 Read from DI pin 2 ODIS Data Output Disable 0 Data in RReg SPI DATA is ignored 1 Data in RReg SPI DATA is shifted out on DO 1 MSTREN Master Mode enable 0 SPI operates in Slave Mode 1 SPI operates in Master Mode 0 CSN_EN Chip Select signal control 0 Chip select enabled 1 Chip selec...

Page 88: ...Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 88 of 206 Apr 21 21 0 CPOL SPI clock polarity 0 Clock line is low when idle 1 Clock line is high when idle ...

Page 89: ... RX buffer of the RYZ012 UART is close to full the RYZ012 sends a signal configurable high or low level through pin RTS to inform the other device that it should stop sending data Similarly if the RYZ012 receives a signal from pin CTS it indicates that the RX buffer of the other device is close to full and that the RYZ012 should stop sending data UART DATA serve to write data into TX buffer or rea...

Page 90: ...T DATA 3 DAT3 rw 0 UART DATA 2 DAT2 rw 0 UART DATA 1 DAT1 rw 0 UART DATA 0 DAT0 rw 0 7 0 15 8 23 16 31 24 DATx UART Data Buffer Read Write Data buffer to corresponding byte 8 1 2 UART CLKDIV UART Clock Divider Configuration Address 0x0094 Reset 0x0fff 7 6 5 4 3 2 1 0 UART CLKDIV 1 DIVEN DIV rw 0 rw 15 UART CLKDIV 0 DIV rw 255 15 DIVEN Enable UART clock divider 0 Disables clock divider 1 Enables cl...

Page 91: ... 24 RXTRIG RX interrupt trigger byte count Number of occupied receive buffer bytes that trigger an interrupt 23 RTSEN Enable RTS 0 Disables RTS signal generation 1 Enables RTS signal generation 22 RTSMEN Enable RTS manual mode 0 Disables RTS manual configuration 1 Enables RTS manual configuration 21 RTSMVAL RTS manual signal level 0 Set RTS signal to LOW level 1 Set RTS signal to HIGH level 20 RTS...

Page 92: ...Disables the CTS signal processing 1 Enables the CTS signal processing 8 CTSI CTS signal inverter 0 The CTS input will be configured as LOW active 1 The CTS input will be configured as HIGH active 7 INTTX Enable TX interrupt 0 Disables TX interrupt 1 Enables TX interrupt 6 INTRX Enable RX interrupt 0 Disables RX interrupt 1 Enables RX interrupt 5 DMATX Enable DMA data processing for sending data T...

Page 93: ...rror indication 1 Enables mask error indication 14 MASKDONE Enable mask done indication 0 Disables mask done indication 1 Enables mask done indication 13 7816EN Enable ISO7816 UART standard 0 Disables ISO7816 UART 1 Enables ISO7816 UART 9 0 TOV Timeout Value Number of UART clock cycles required for one transaction This value should be computed as TOV BRC 1 bits per byte transaction byte count 8 1 ...

Page 94: ...X mask error detected 1 TX mask error detected Write 1 to clear 3 IRQ RX TX interrupt indication 0 No RX TX interrupt detected 1 RX TX buffer interrupt detected 8 1 7 UART TXRX_STATUS UART RX TX Status Address 0x009e Reset 0x00 7 6 5 4 3 2 1 0 UART TXRX_STATUS RSVD RXBUFIRQ RXDONE TXBUFIRQ TXDONE r 0 r 0 r 0 r 0 r 0 3 RXBUFIRQ RX buffer interrupt indication 0 No RX buffer interrupt detected 1 RX b...

Page 95: ...port four modes Mode 0 System Clock Mode Mode 1 GPIO Trigger Mode Mode 2 GPIO Pulse Width Mode and Mode 3 Tick Mode which are selectable through TIMER CTRL MODE0 to TIMER CTRL MODE2 to the corresponding Timer Timer2 can also be configured as watchdog to monitor proper firmware execution 10 1 1 Mode 0 System Clock Mode In Mode 0 the system clock is employed as clock source After the timer is enable...

Page 96: ...R or GPIOx T2 specify the GPIO that generates the control signals for Timer 0 Timer 1 and Timer 2 respectively When the Timer is enabled Timer Tick is triggered by a positive negative configurable edge of GPIO pulse Then Timer Tick that is counting value is increased by 1 on each positive edge of system clock Generally the initial Tick value should be set to 0 The GPIOx INTPOL register specifies t...

Page 97: ...e When the watchdog is triggered the chip is reset 10 1 5 1 Watchdog Timer Configuration Example 1 Clear Timer 2 Tick value by setting TIMER TICK2 to zero 2 Configure the Watchdog Capture value TIMER CTRL WDCAPT to the appropriate timeout value and enable the watchdog by setting TIMER CTRL WDEN to 1b 1 3 Enable Timer 2 by setting TIMER CTRL EN2 to 1b 1 4 Periodically reset Timer 2 Tick value befor...

Page 98: ... CTRL 0 MODE2 EN2 MODE1 EN1 MODE0 EN0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 23 WDEN Watchdog enable 0 Disables Watchdog capture 1 Enables Watchdog capture 22 9 WDCAPT Watchdog capture value 8 7 MODE2 Timer 2 mode selection Last significant bit of MODE2 00 Using SCLK 01 Using GPIO 10 Count width of GPI 11 Timer ticks 6 EN2 Timer 2 enable 0 Disables Timer 2 1 Enables Timer 2 5 4 MODE1 Timer 1 mode selection...

Page 99: ...N0 Timer 0 enable 0 Disables Timer 0 1 Enables Timer 0 10 3 2 TIMER STATUS Timer Status Address 0x0623 Reset 0x00 7 6 5 4 3 2 1 0 TIMER STATUS RSVD TS2 TS1 TS0 RSVD rw 0 rw1 0 rw1 0 rw1 0 rw 0 3 TS2 Timer 2 status 0 Timer 2 did not trigger 1 Timer 2 triggered Write 1 to clear 2 TS1 Timer 1 status 0 Timer 1 did not trigger 1 Timer 1 triggered Write 1 to clear 1 TS0 Timer 0 status 0 Timer 0 did not ...

Page 100: ...0x0624 Reset 0x00000000 7 6 5 4 3 2 1 0 TIMER CAPT0 3 CAPT0 rw 0 TIMER CAPT0 2 CAPT0 rw 0 TIMER CAPT0 1 CAPT0 rw 0 TIMER CAPT0 0 CAPT0 rw 0 31 0 CAPT0 Timer 0 Capture Value 10 3 4 TIMER CAPT1 Timer 1 Capture Address 0x0628 Reset 0x00000000 7 6 5 4 3 2 1 0 TIMER CAPT1 3 CAPT1 rw 0 TIMER CAPT1 2 CAPT1 rw 0 TIMER CAPT1 1 CAPT1 rw 0 TIMER CAPT1 0 CAPT1 rw 0 31 0 CAPT1 Timer 1 Capture Value ...

Page 101: ...62c Reset 0x00000000 7 6 5 4 3 2 1 0 TIMER CAPT2 3 CAPT2 rw 0 TIMER CAPT2 2 CAPT2 rw 0 TIMER CAPT2 1 CAPT2 rw 0 TIMER CAPT2 0 CAPT2 rw 0 31 0 CAPT2 Timer 2 Capture Value 10 3 6 TIMER TICK0 Timer 0 Tick Counter Address 0x0630 Reset 0x00000000 7 6 5 4 3 2 1 0 TIMER TICK0 3 TICK0 rw 0 TIMER TICK0 2 TICK0 rw 0 TIMER TICK0 1 TICK0 rw 0 TIMER TICK0 0 TICK0 rw 0 31 0 TICK0 Timer 0 Counter Value ...

Page 102: ...R TICK2 2 TICK2 rw 0 TIMER TICK2 1 TICK2 rw 0 TIMER TICK2 0 TICK2 rw 0 31 0 TICK2 Timer 2 Counter Value 10 4 System Timer The RYZ012 also supports a System Timer As introduced in System Timer Clock the clock frequency for System Timer is fixed as 16MHz irrespective of system clock In suspend mode both System Timer and Timer 0 Timer 2 stop counting and 32K Timer starts counting When the chip restor...

Page 103: ...5 4 3 2 1 0 SYSTIM CNT 3 CNT rw 0 SYSTIM CNT 2 CNT rw 0 SYSTIM CNT 1 CNT rw 0 SYSTIM CNT 0 CNT RSVD rw 0 rw 0 31 3 CNT This is the System Timer counter value Write to set initial value 10 5 2 SYSTIM CTRL System Timer Control Address 0x074c Reset 0x0090 7 6 5 4 3 2 1 0 SYSTIM CTRL 1 RSVD rw 0 SYSTIM CTRL 0 RSVD IRQEN RSVD rw 36 rw 0 rw 0 1 IRQEN System Timer Interrupt Enable 0 Disables System timer...

Page 104: ...l can be inverted through register PWM POL independently for each channel In addition the polarity of the direct output and the inverted output can be controlled through registers PWM DPOL and PWM IPOL respectively Figure 18 PWM PWM Output Generation The individual PWM channels are enabled through register PWM EN When the PWM is disabled the corresponding output turns low immediately An interrupti...

Page 105: ...set If the interrupt is enabled in register PWM MASK0 CNT0 an interrupt request is sent to the interrupt controller The interrupt flag is cleared by writing 1b 1 to it Figure 19 Counting Mode Counting mode also serves to stop IR mode gracefully See IR Mode for details 11 1 3 IR Mode Only PWM0 supports IR mode PWM MODE MODE should be set as 4b 0011 to select PWM0 IR mode IR Mode is similar to Count...

Page 106: ... 3 2 1 0 PWM EN 1 RSVD CH0EN rw 0 rw 0 PWM EN 0 RSVD CH5EN CH4EN CH3EN CH2EN CH1EN RSVD rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 8 CH0EN Enable PWM0 0 Disables PWM0 1 Enables PWM0 5 CH5EN Enable PWM5 0 Disables PWM5 1 Enables PWM5 4 CH4EN Enable PWM4 0 Disables PWM4 1 Enables PWM4 3 CH3EN Enable PWM3 0 Disables PWM3 1 Enables PWM3 2 CH2EN Enable PWM2 0 Disables PWM2 1 Enables PWM2 1 CH1EN Enable PWM1 0 ...

Page 107: ...3 Reset 0x00 7 6 5 4 3 2 1 0 PWM MODE RSVD MODE rw 0 rw 0 3 0 MODE PWM0 mode selection 0000 Select PWM0 Continuous Mode 0001 Select PWM0 Counting Mode 0011 Select PWM0 IR Mode 0111 Select PWM0 IR FIFO Mode 1111 Select PWM0 IR DMA FIFO Mode 11 2 4 PWM DPOL PWMx Pin Output Inversion Address 0x0784 Reset 0x00 7 6 5 4 3 2 1 0 PWM DPOL RSVD DPOL5 DPOL4 DPOL3 DPOL2 DPOL1 DPOL0 rw 0 rw 0 rw 0 rw 0 rw 0 r...

Page 108: ...the output polarity of the corresponding inverted PWM output pin PWMx_N 0 PWMx_N is not inverted 1 PWMx_N is inverted 11 2 6 PWM POL PWM Polarity Address 0x0786 Reset 0x00 7 6 5 4 3 2 1 0 PWM POL RSVD POL5 POL4 POL3 POL2 POL1 POL0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 1 2 3 4 5 POLx Configures the PWM frame polarity 0 Frame starts with high level 1 Frame starts with low level 11 2 7 PWM TCMP0 PWM0 ...

Page 109: ... 6 5 4 3 2 1 0 PWM TMAX0 1 VAL rw 0 PWM TMAX0 0 VAL rw 0 15 0 VAL PWM0 cycle time value 11 2 9 PWM TCMP1 PWM1 Capture Mode Time Address 0x0798 Reset 0x0000 7 6 5 4 3 2 1 0 PWM TCMP1 1 VAL rw 0 PWM TCMP1 0 VAL rw 0 15 0 VAL PWM1 high time or low time value 11 2 10 PWM TMAX1 PWM1 Maximum Cycle Time Address 0x079a Reset 0x0000 7 6 5 4 3 2 1 0 PWM TMAX1 1 VAL rw 0 PWM TMAX1 0 VAL rw 0 15 0 VAL PWM1 cy...

Page 110: ... 3 2 1 0 PWM TCMP2 1 VAL rw 0 PWM TCMP2 0 VAL rw 0 15 0 VAL PWM2 high time or low time value 11 2 12 PWM TMAX2 PWM2 Maximum Cycle Time Address 0x079e Reset 0x0000 7 6 5 4 3 2 1 0 PWM TMAX2 1 VAL rw 0 PWM TMAX2 0 VAL rw 0 15 0 VAL PWM2 cycle time value 11 2 13 PWM TCMP3 PWM3 Capture Mode Time Address 0x07a0 Reset 0x0000 7 6 5 4 3 2 1 0 PWM TCMP3 1 VAL rw 0 PWM TCMP3 0 VAL rw 0 15 0 VAL PWM3 high ti...

Page 111: ... 6 5 4 3 2 1 0 PWM TMAX3 1 VAL rw 0 PWM TMAX3 0 VAL rw 0 15 0 VAL PWM3 cycle time value 11 2 15 PWM TCMP4 PWM4 Capture Mode Time Address 0x07a4 Reset 0x0000 7 6 5 4 3 2 1 0 PWM TCMP4 1 VAL rw 0 PWM TCMP4 0 VAL rw 0 15 0 VAL PWM4 high time or low time value 11 2 16 PWM TMAX4 PWM4 Maximum Cycle Time Address 0x07a6 Reset 0x0000 7 6 5 4 3 2 1 0 PWM TMAX4 1 VAL rw 0 PWM TMAX4 0 VAL rw 0 15 0 VAL PWM4 c...

Page 112: ... PWM TCMP5 1 VAL rw 0 PWM TCMP5 0 VAL rw 0 15 0 VAL PWM5 high time or low time value 11 2 18 PWM TMAX5 PWM5 Maximum Cycle Time Address 0x07aa Reset 0x0000 7 6 5 4 3 2 1 0 PWM TMAX5 1 VAL rw 0 PWM TMAX5 0 VAL rw 0 15 0 VAL PWM5 cycle time value 11 2 19 PWM PNUM0 PWM0 Pulse Number Address 0x07ac Reset 0x0000 7 6 5 4 3 2 1 0 PWM PNUM0 1 RSVD VAL rw 0 rw 0 PWM PNUM0 0 VAL rw 0 13 0 VAL PWM0 Pulse numb...

Page 113: ...pt 1 Enables interrupt 6 FR4 Enable PWM4 frame interrupt 0 Disables interrupt 1 Enables interrupt 5 FR3 Enable PWM3 frame interrupt 0 Disables interrupt 1 Enables interrupt 4 FR2 Enable PWM2 frame interrupt 0 Disables interrupt 1 Enables interrupt 3 FR1 Enable PWM1 frame interrupt 0 Disables interrupt 1 Enables interrupt 2 FR0 Enable PWM0 frame interrupt 0 Disables interrupt 1 Enables interrupt 1 ...

Page 114: ...ion CNT4 TMAX4 0 No interrupt detected 1 Interrupt detected Write 1 to clear 5 FR3 PWM3 cycle done interrupt indication CNT3 TMAX3 0 No interrupt detected 1 Interrupt detected Write 1 to clear 4 FR2 PWM2 cycle done interrupt indication CNT2 TMAX2 0 No interrupt detected 1 Interrupt detected Write 1 to clear 3 FR1 PWM1 cycle done interrupt indication CNT1 TMAX1 0 No interrupt detected 1 Interrupt d...

Page 115: ...11 2 22 PWM MASK1 PWM Interrupt Mask Address 0x07b2 Reset 0x00 7 6 5 4 3 2 1 0 PWM MASK1 RSVD FIFOCNT rw 0 rw 0 0 FIFOCNT Enable PWM0 FIFO count interrupt FIFO mode 0 Disables interrupt 1 Enables interrupt 11 2 23 PWM INT1 PWM Interrupt Status Address 0x07b3 Reset 0x00 7 6 5 4 3 2 1 0 PWM INT1 RSVD FIFOCNT rw 0 rw 0 0 FIFOCNT PWM0 FIFO count interrupt FIFO mode indication FIFO_NUM FIFO_NUM_LVL 0 N...

Page 116: ...07b4 Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT0 1 VAL r 0 PWM CNT0 0 VAL r 0 15 0 VAL PWM0 counter value 11 2 25 PWM CNT1 PWM1 Counter Value Address 0x07b6 Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT1 1 VAL r 0 PWM CNT1 0 VAL r 0 15 0 VAL PWM1 counter value 11 2 26 PWM CNT2 PWM2 Counter Value Address 0x07b8 Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT2 1 VAL r 0 PWM CNT2 0 VAL r 0 15 0 VAL PWM2 counter value ...

Page 117: ...07ba Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT3 1 VAL r 0 PWM CNT3 0 VAL r 0 15 0 VAL PWM3 counter value 11 2 28 PWM CNT4 PWM4 Counter Value Address 0x07bc Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT4 1 VAL r 0 PWM CNT4 0 VAL r 0 15 0 VAL PWM4 counter value 11 2 29 PWM CNT5 PWM5 Counter Value Address 0x07be Reset 0x0000 7 6 5 4 3 2 1 0 PWM CNT5 1 VAL r 0 PWM CNT5 0 VAL r 0 15 0 VAL PWM5 counter value ...

Page 118: ...AL r 0 15 0 VAL PWM0 pulse count value 11 2 31 PWM TCMP0_SHADOW PWM0 Shadow Capture Mode Time Address 0x07c4 Reset 0x5555 7 6 5 4 3 2 1 0 PWM TCMP0_SHADOW 1 VAL rw 85 PWM TCMP0_SHADOW 0 VAL rw 85 15 0 VAL PWM0 high or low time in IR FIFO or DMA FIFO mode 11 2 32 PWM TMAX0_SHADOW PWM0 Maximum Shadow Cycle Time Address 0x07c6 Reset 0x0000 7 6 5 4 3 2 1 0 PWM TMAX0_SHADOW 1 VAL rw 0 PWM TMAX0_SHADOW ...

Page 119: ..._ENTRY 0 VAL rw 0 31 0 VAL FIFO data entry byte 0 in IR FIFO mode 11 2 34 PWM FIFO_NUM_LVL FIFO Interrupt Trigger Entry Address 0x07cc Reset 0x00 7 6 5 4 3 2 1 0 PWM FIFO_NUM_LVL VAL rw 0 7 0 VAL FIFO interrupt trigger byte count 11 2 35 PWM FIFO_SR PWM FIFO Status Address 0x07cd Reset 0x00 7 6 5 4 3 2 1 0 PWM FIFO_SR RSVD FULL EMPTY DAT r 0 r 0 r 0 r 0 5 FULL FIFO full indication 0 FIFO data buff...

Page 120: ...15 4 R15UH0002EU0103 Rev 1 03 Page 120 of 206 Apr 21 21 3 0 DAT FIFO data count Current number of bytes in the FIFO 11 2 36 PWM FIFO_CLR PWM FIFO Clear Address 0x07ce Reset 0x00 7 6 5 4 3 2 1 0 PWM FIFO_CLR RSVD CLR w1 0 w1 0 0 CLR Clear data FIFO 0 Not used 1 FIFO data buffer is cleared ...

Page 121: ...he PGA After implementing AD conversion for selected AMIC input signal data of 3 analog channels CH0 CH2 is generated Data of CH0 CH1 is sent to the audio input processing module while data of CH2 is directly written into the FIFO 12 1 2 DMIC Input Stereo digital microphone DMIC interface is also supported in the RYZ012 AUDIO_IN DFIFOAIN AISEL should be set as 2b 11 to select DMIC as audio input T...

Page 122: ...e maximum data number for DFIFO0 Suppose AUDIO_IN DFIFO0_DEPTH is set as 0x01 then the DFIFO0 depth is 4 words that is 16 bytes Current data number the difference value of write pointer and read pointer in DFIFO0 can be read from AUDIO_IN DFIFO0_NUM The user can check current DFIFO0 read pointer write pointer location by reading AUDIO_IN DFIFO0_RPTR or AUDIO_IN DFIFO1_RPTR When current data number...

Page 123: ...digital mode applies to all audio input types In analog mode input volume level is regulated via PGA while in digital mode input volume level is regulated via Multiplier Divider 12 2 5 1 Automatic Regulation in Analog Mode For automatic regulation in Analog Mode AUDIO_IN ALC_CFG ANSEL should be set as 1b 1 and AUDIO_IN ALC_VOL_L MODE and AUDIO_IN ALC_VOL_R MODE should be set as 1b 1 to enable auto...

Page 124: ...gital gain is compared with the high volume target AUDIO_IN ALC_VOL_THH and the low volume target AUDIO_IN ALC_VOL_THL Meanwhile it is compared with the volume noise level AUDIO_IN ALC_VOL_THN to judge the noise signal and help regulate the digital gain The digital gain automatically adjusts according to the comparison results and it should be in the range from minimum digital gain AUDIO_IN ALC_VO...

Page 125: ...0 VAL FIFO0 base address byte 0 12 3 2 AUDIO_IN DFIFO0_BADR1 DFIFO0 Base Address Address 0x0b01 Reset 0x40 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO0_BADR1 VAL rw 64 7 0 VAL FIFO0 base address byte 1 12 3 3 AUDIO_IN DFIFO0_DEPTH DFIFO0 Depth Address 0x0b02 Reset 0x7f 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO0_DEPTH VAL rw 127 7 0 VAL FIFO0DEPTH FIFO0_DEPTH 4 words 12 3 4 AUDIO_IN DFIFO0_BADR2 DFIFO0 Base Address Addres...

Page 126: ...ess byte 0 12 3 6 AUDIO_IN DFIFO1_BADR1 DFIFO1 Base Address Address 0x0b05 Reset 0x48 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO1_BADR1 VAL rw 72 7 0 VAL FIFO1 base address byte 1 12 3 7 AUDIO_IN DFIFO1_DEPTH DFIFO1 Depth Address 0x0b06 Reset 0x7f 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO1_DEPTH VAL rw 127 7 0 VAL FIFO1DEPTH FIFO1_DEPTH 4 words 12 3 8 AUDIO_IN DFIFO1_BADR2 DFIFO1 Base Address Address 0x0b07 Reset 0x04 7...

Page 127: ...ss byte 0 12 3 10 AUDIO_IN DFIFO2_BADR1 DFIFO2 Base Address Address 0x0b09 Reset 0x3c 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO2_BADR1 VAL rw 60 7 0 VAL FIFO2 base address byte 1 12 3 11 AUDIO_IN DFIFO2_DEPTH DFIFO2 Depth Address 0x0b0a Reset 0x3f 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO2_DEPTH VAL rw 63 7 0 VAL FIFO2DEPTH FIFO2_DEPTH 4 words 12 3 12 AUDIO_IN DFIFO2_BADR2 DFIFO2 Base Address Address 0x0b0b Reset 0x04 ...

Page 128: ... AUDIO_IN DFIFO0_HLEV DFIFO0 Interrupt Level Address 0x0b0d Reset 0x60 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO0_HLEV VAL rw 96 7 0 VAL FIFO0 interrupt trigger high level byte count 12 3 15 AUDIO_IN DFIFO1_HLEV DFIFO1 Interrupt Level Address 0x0b0e Reset 0x20 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO1_HLEV VAL rw 32 7 0 VAL FIFO1 interrupt trigger high level byte count 12 3 16 AUDIO_IN DFIFO2_HLEV DFIFO2 Interrupt Lev...

Page 129: ...x interrupt 6 HIGH1 FIFO1 high interrupt enable 12 Disables FIFOx interrupt 13 Enables FIFOx interrupt 5 HIGH0 FIFO0 high interrupt enable 10 Disables FIFOx interrupt 11 Enables FIFOx interrupt 4 LOW0 FIFO0 low interrupt enable 8 Disables FIFOx interrupt 9 Enables FIFOx interrupt 3 AO0 Enable audio output of FIFO0 6 Disables FIFOx output 7 Enables FIFOx output 2 AI2 Enable audio input of FIFO2 4 D...

Page 130: ...dge of clock 6 EEN0 dmic_raise_chn_not_en 0 Disables DMICx sampling at rising edge of clock 1 Enables DMICx sampling at rising edge of clock 5 DECFEN Enable input decimation filter low active 0 Enables input filter 1 Disables input filter 4 AIMODE Audio input mode selection 0 Select audio stereo input 1 Select audio mono input 3 2 AISEL Audio input selection 00 no available 01 Select I2S input 10 ...

Page 131: ...H0M LOW0M HIGH2A HIGH1A HIGH0A LOW0A rw1c 0 rw1c 0 rw1c 0 rw1c 0 r 0 r 0 r 0 r 0 7 HIGH2M FIFO2 high level interrupt indication 0 No interrupt detected 1 Interrupt detected Write 1 to clear 6 HIGH1M FIFO1 high level interrupt indication 0 No interrupt detected 1 Interrupt detected Write 1 to clear 5 HIGH0M FIFO0 high level interrupt indication 0 No interrupt detected 1 Interrupt detected Write 1 t...

Page 132: ...y hardware when number of items in FIFO0 is below DFIFO0_HLEV 0 LOW0A FIFO0 low level interrupt indication 0 No interrupt detected 1 Interrupt detected Cleared by hardware when number of items in FIFO0 is above DFIFO0_LLEV 12 3 21 AUDIO_IN DFIFO0_RPTR Read FIFO0 PTR Address 0x0b14 Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO0_RPTR 1 RSVD VAL ro 0 ro 0 AUDIO_IN DFIFO0_RPTR 0 VAL ro 0 11 0 VAL Read F...

Page 133: ...D VAL ro 0 ro 0 AUDIO_IN DFIFO1_RPTR 0 VAL ro 0 11 0 VAL Read FIFO1 PTR value 12 3 24 AUDIO_IN DFIFO1_WPTR Write FIFO1 PTR Address 0x0b1a Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO1_WPTR 1 RSVD VAL ro 0 ro 0 AUDIO_IN DFIFO1_WPTR 0 VAL ro 0 11 0 VAL Write FIFO1 PTR value 12 3 25 AUDIO_IN DFIFO2_RPTR Read FIFO2 Address 0x0b1c Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO2_RPTR 1 RSVD VAL ro 0 ro 0 AU...

Page 134: ...1 RSVD VAL ro 0 ro 0 AUDIO_IN DFIFO2_WPTR 0 VAL ro 0 11 0 VAL Write FIFO2 PTR value 12 3 27 AUDIO_IN DFIFO0_NUM Number FIFO0 Address 0x0b20 Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO0_NUM 1 VAL ro 0 AUDIO_IN DFIFO0_NUM 0 VAL ro 0 15 0 VAL Current number of bytes FIFO0 12 3 28 AUDIO_IN DFIFO1_NUM Number FIFO1 Address 0x0b24 Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO1_NUM 1 VAL ro 0 AUDIO_IN DFIFO...

Page 135: ... 1 VAL ro 0 AUDIO_IN DFIFO2_NUM 0 VAL ro 0 15 0 VAL Current number of bytes FIFO2 12 3 30 AUDIO_IN DFIFO_MANUAL DFIFO Manual Mode Address 0x0b2c Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO_MANUAL RSVD EN rw 0 rw 0 0 EN DFIFO Manual Mode 0 FIFO automatic mode 1 FIFO manual mode 12 3 31 AUDIO_IN DFIFO_MAN_DAT0 DFIFO Manual Mode Data Address 0x0b30 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO_MAN_DA T0 VA...

Page 136: ...4 3 2 1 0 AUDIO_IN DFIFO_MAN_DA T1 VAL w 0 7 0 VAL FIFO manual mode data input byte 1 12 3 33 AUDIO_IN DFIFO_MAN_DAT2 DFIFO Manual Mode Data Address 0x0b32 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO_MAN_DA T2 VAL w 0 7 0 VAL FIFO manual mode data input byte 2 12 3 34 AUDIO_IN DFIFO_MAN_DAT3 DFIFO Manual Mode Data Address 0x0b33 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN DFIFO_MAN_DA T3 VAL w 0 7 0 VAL FIF...

Page 137: ...0 Disables audio input channel swap 1 Enables audio input channel swap 3 ADCTRIM Enable bypass ADC trim 0 Disables bypass ADC trim 1 Enables bypass ADC trim 2 ADCSIGN Enable ADC signed byte 0 Disables ADC signed byte 1 Enables ADC signed byte 1 ADCOPT Enable ADC 64 63 option 0 Disables ADC 64 63 option 1 Enables ADC 64 63 option 0 VALIDEN Enable ADC valid indication 0 Disables ADC valid indication...

Page 138: ...ias 12 3 38 AUDIO_IN ALC_FLT_CTRL ALC Filter Control Address 0x0b40 Reset 0xfb 7 6 5 4 3 2 1 0 AUDIO_IN ALC_FLT_CTRL DSEN LPFBYP ALCBYP HPFBYP HPFADJ rw 1 rw 1 rw 1 rw 1 rw 11 7 DSEN Enable double down sampling 0 Disables double down sampling 1 Enables double down sampling 6 LPFBYP LPF Bypass 0 LPF is enabled 1 LPF is bypassed 5 ALCBYP ALC Bypass Control 0 ALC is enabled 1 ALC is bypassed 4 HPFBYP...

Page 139: ... 0 GAIN 6 0 Minimum gain limit in automatic mode 5 0 Digital gain in manual mode 12 3 40 AUDIO_IN ALC_VOL_R ALC Right Channel Setting Address 0x0b42 Reset 0x20 7 6 5 4 3 2 1 0 AUDIO_IN ALC_VOL_R MODE GAIN rw 0 rw 32 7 MODE Mode selection 0 Select automatic mode 1 Select manual mode 6 0 GAIN 6 0 Minimum gain limit in automatic mode 5 0 Digital gain in manual mode 12 3 41 AUDIO_IN ALC_VOL_H Maximum ...

Page 140: ...of high volume target in automatic mode 12 3 43 AUDIO_IN ALC_VOL_THL PGA LOW volume Target Address 0x0b46 Reset 0x40 7 6 5 4 3 2 1 0 AUDIO_IN ALC_VOL_THL RSVD INT FRAC rw 0 rw 32 rw 0 6 1 INT Set integer part dB of low volume target in automatic mode 0 FRAC Set fractional part dB of low volume target in automatic mode 12 3 44 AUDIO_IN ALC_VOL_THN PGA Noise Level Target Address 0x0b48 Reset 0x02 7 ...

Page 141: ... mode of left channel 12 3 46 AUDIO_IN ALC_VOL_R_R PGA Right Channel Gain Address 0x0b4e Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN ALC_VOL_R_R GAIN r 0 7 0 GAIN Current digital gain volume in automatic manual mode of right channel 12 3 47 AUDIO_IN ALC_PEAK_TICK_L Peak Tick Address 0x0b50 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN ALC_PEAK_TICK _L TICK0 rw 0 7 0 TICK0 Peak tick byte 0 12 3 48 AUDIO_IN ALC_PEAK_...

Page 142: ...imum 0 Disables vad maximum 1 Enables vad maximum 3 TICKCLR Clear ALC_PEAK_TICK 0 Not used 1 ALC_PEAK_TICK bytes will be cleared If ALC_PEAK_TICK is cleared the bit is automatically reset 2 IIRAEN Enable analog IIR 0 Disables analog IIR 1 Enables analog IIR 1 IIRVEN Enable vad IIR 0 Disables vad IIR 1 Enables vad IIR 0 ANSEL Analog mode selection 0 Select digital mode 1 Select analog mode 12 3 50 ...

Page 143: ...UDIO_IN ALC_INC_SPD PGA Gain Increase Speed Address 0x0b57 Reset 0x0a 7 6 5 4 3 2 1 0 AUDIO_IN ALC_INC_SPD SPD rw 10 7 0 SPD PGA gain increase speed in automatic mode 12 3 53 AUDIO_IN ALC_INC_MAX PGA Maximum Gain Increase Address 0x0b58 Reset 0x03 7 6 5 4 3 2 1 0 AUDIO_IN ALC_INC_MAX RSVD MASK rw 0 rw 3 6 0 MASK PGA maximum gain increase of a peak tick cycle in automatic mode 12 3 54 AUDIO_IN ALC_...

Page 144: ...ecrease Speed noise Address 0x0b5b Reset 0x06 7 6 5 4 3 2 1 0 AUDIO_IN ALC_NOI_SPD SPD rw 6 7 0 SPD PGA gain decrease speed in automatic mode if there is noise 12 3 57 AUDIO_IN ALC_NOI_MAX PGA Maximum Gain Decrease noise Address 0x0b5c Reset 0x06 7 6 5 4 3 2 1 0 AUDIO_IN ALC_NOI_MAX RSVD MAX rw 0 rw 6 6 0 MAX PGA maximum gain decrease of a peak tick cycle in automatic mode if there is noise 12 3 5...

Page 145: ..._IN PGA_MAN_SPD PGA Gain Manual Increase Speed Address 0x0b60 Reset 0x40 7 6 5 4 3 2 1 0 AUDIO_IN PGA_MAN_SPD SPD rw 64 7 0 SPD Set speed for PGA gain to reach the target gain value 12 3 61 AUDIO_IN PGA_MAN_TARGET_L PGA Left Channel Manual Target Address 0x0b61 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN PGA_MAN_TAR GET_L TACC TGAIN r 0 rw 0 7 TACC Target left channel value indication 0 PGA target left ch...

Page 146: ...uted 1 Channel is muted 6 0 VAL Current left channel value in manual mode 12 3 63 AUDIO_IN PGA_FIX_VALUE PGA Fixed Value Address 0x0b63 Reset 0x80 7 6 5 4 3 2 1 0 AUDIO_IN PGA_FIX_VALUE FGEN FGAIN rw 1 rw 0 7 FGEN Enable fix PGA gain 0 Disables fix PGA gain 1 Enables fix PGA gain 6 0 FGAIN Set PGA gain fix value 12 3 64 AUDIO_IN PGA_R_L Change PGA Channel Control Address 0x0b64 Reset 0x00 7 6 5 4 ...

Page 147: ...as reached in manual mode 6 0 TGAIN Set PGA target right channel gain value in manual mode 12 3 66 AUDIO_IN PGA_VALUE_R PGA Right Channel Value Address 0x0b66 Reset 0x00 7 6 5 4 3 2 1 0 AUDIO_IN PGA_VALUE_R MUTE VAL r 0 r 0 7 MUTE Right channel mute control 0 Channel is not muted 1 Channel is muted 6 0 VAL Current right channel value in manual mode 12 4 Audio Output Path Audio output path mainly i...

Page 148: ...8kHz and the working clock of SDM I2S is FI2S then the interpolation ratio is given as follows 48KHz FI2S BS 0x80000 Where BS is configured in AUDIO_OUT I2SCLK BSL and AUDIO_OUT ASCL_STEP BSH Linear interpolation or delay interpolation is used as shown below Figure 24 Linear Interpolation Figure 25 Delay Interpolation 12 4 2 Sigma Delta Modulator SDM The SDM takes 16 bits audio data from SRAM and ...

Page 149: ...nd AUDIO_OUT PN_CTRL PN1LEN should be set to 1b 1 2 To select the PN sequence with Shaping as input AUDIO_OUT PN_CTRL PNLEN should be set to 1b 0 and AUDIO_OUT PWM_CTRL LSEN AUDIO_OUT PN_CTRL PN2LEN and AUDIO_OUT PN_CTRL PN1LEN should be set to 1b 1 When PN sequence or PN with Shaping is used AUDIO_OUT PN_CTRL BPN1L and AUDIO_OUT PN_CTRL BPN2L determines the number of bits ranging from 0 to 16 use...

Page 150: ...bles HPF 1 Enables HPF 6 GRPEN GPR player enable control bit 0 Disables GRP 1 Enables GRP 5 I2S_EN I2S interface enable control bit 0 Disables I2S interface 1 Enables I2S interface 4 I2S_REC I2S recorder enable control bit 0 Disables I2S recorder 1 Enables I2S recorder 3 ISO_PLY ISO player enable control bit 0 Disables ISO player 1 Enables ISO player 2 SDM_PLY SDM player enable control bit 0 Disab...

Page 151: ... QEN rw 0 rw 16 rw 0 rw 0 7 MUTE Volume mute control 0 Disables mute volume 1 Enables mute volume 6 2 SHIFT Current volume shift left 1 HEN Enable half volume add 0 Disables half volume increase 1 Enables half volume increase 0 QEN Enable quarter volume add 0 Disables quarter volume increase 1 Enables quarter volume increase 12 5 4 AUDIO_OUT PWM_CTRL Audio Out PWM Control Address 0x0563 Reset 0x64...

Page 152: ...L Interpolation selection 0 Select delay interpolation 1 Select linear interpolation 1 EN Enable PWM 0 Disables PWM 1 Enables PWM 0 MULF PWM multiply 0 No doubling the PWM 1 Doubling the PWM 12 5 5 AUDIO_OUT ASCL_TUNE Tune Step Address 0x0564 Reset 0x01 7 6 5 4 3 2 1 0 AUDIO_OUT ASCL_TUNE TBS rw 1 7 0 TBS Tune step for rate matching block 12 5 6 AUDIO_OUT I2SCLK I2S Clock configuration Address 0x0...

Page 153: ..._CTRL 3 RSVD PNREN PNLEN BPN2R rw 0 rw 0 rw 0 rw 0 AUDIO_OUT PN_CTRL 2 RSVD EXSMD CLKI BPN1R rw 0 rw 0 rw 0 rw 16 AUDIO_OUT PN_CTRL 1 RSVD PN1REN PN2REN BPN2L rw 0 rw 1 rw 0 rw 0 AUDIO_OUT PN_CTRL 0 RSVD PN1LEN PN2LEN BPN1L rw 0 rw 1 rw 0 rw 16 30 PNREN Right Channel PN Selection 0 Right channel use PN generator 1 Right channel use constant value 29 PNLEN Left Channel PN Selection 0 Left channel u...

Page 154: ...channel 1 Enables PN generator 2 of right channel 12 8 BPN2L Left channel PN2 bits Range from 0 to 16 6 PN1LEN Left channel PN1 enable 0 Disables PN generator 1 of left channel 1 Enables PN generator 1 of left channel 5 PN2LEN Left channel PN2 enable 0 Disables PN generator 2 of left channel 1 Enables PN generator 2 of left channel 4 0 BPN1L Left channel PN1 bits Range from 0 to 16 12 5 9 AUDIO_OU...

Page 155: ...gy and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 155 of 206 Apr 21 21 12 5 10 AUDIO_OUT CONST_RIGHT Constant Right Channel Address 0x056e Reset 0x0000 7 6 5 4 3 2 1 0 AUDIO_OUT CONST_RIGH T 1 CCHR rw 0 AUDIO_OUT CONST_RIGH T 0 CCHR rw 0 15 0 CCHR DC input constant of right channel ...

Page 156: ...g pin must be activated as input IE and deactivated as output ODIS Table 12 Input Pin Selection CHA CHB Pin 2 PB6 3 PB7 4 PC2 5 PC3 7 PD7 13 2 Common Mode and Double Accuracy Mode QDEC DOUBLE EN serves to select Common Mode or double accuracy mode In Common Mode for each wheel rolling step two pulse edges rising edge or falling edge are generated If QDEC DOUBLE EN is cleared to select common mode ...

Page 157: ...unter data into the QDEC COUNT before the register is read The register is cleared automatically after it has been read Figure 29 Read Real time Counting Value 13 4 QDEC Reset QDEC RST serves to reset the QDEC The QDEC Counter value is cleared to zero 13 5 Other Configuration The QDEC supports hardware debouncing QDEC GC FTIME serves to set the filtering window duration All jitter with period less...

Page 158: ...alling edges 2 n 1 clk_32kHz QDEC module works based on 32kHz clock to ensure it can work in suspend mode The debouncing function regards any signal with a width lower than the threshold that is 2 n 1 clk_32kHz as jitter Therefore effective signals input from Channel A and B should contain high low level with width Thpw Tlpw more than the threshold The 2n clk_32kHz clock is used to synchronize inp...

Page 159: ...edge number counting value Register will be cleared by reading 13 7 2 QDEC GC QDEC General Configuration Address 0x00d1 Reset 0x00 7 6 5 4 3 2 1 0 QDEC GC RSVD SHU POL RSVD FTIME rw 0 rw 0 rw 0 rw 0 rw 0 5 SHU Enable Shuttle Mode which allows non overlapping two phase signals 0 Disables Shuttle Mode 1 Enables Shuttle Mode 4 POL Input signal polarity selection 0 Input signal is initial LOW 1 Input ...

Page 160: ...elect Port A Pin 2 1 Select Port A Pin A 2 Select Port B Pin 6 3 Select Port B Pin 7 4 Select Port C Pin 2 5 Select Port C Pin 3 6 Select Port D Pin 6 7 Select Port D Pin 7 13 7 4 QDEC CHB QDEC Input Channel B Address 0x00d3 Reset 0x01 7 6 5 4 3 2 1 0 QDEC CHB RSVD INSEL rw 0 rw 1 2 0 INSEL Input pin select for channel B 0 Select Port A Pin 2 1 Select Port A Pin A 2 Select Port B Pin 6 3 Select Po...

Page 161: ...when QDEC was reset 1 If bit is set to 1 data can be loaded 13 7 6 QDEC DOUBLE QDEC Mode Configuration Address 0x00d7 Reset 0x00 7 6 5 4 3 2 1 0 QDEC DOUBLE RSVD EN rw 0 rw 0 0 EN QDEC Mode selection 0 Enables common mode 1 Enables double accuracy mode 13 7 7 QDEC DATA_LOAD QDEC Data Status Address 0x00d8 Reset 0x00 7 6 5 4 3 2 1 0 QDEC DATA_LOAD RSVD LOAD rw 0 rw 0 0 LOAD Data load status 0 Is se...

Page 162: ...ate The length of Set state for left right and Misc channel is configurable through the analog register SAR_ADC CAPCFG ST Set state duration is defined as Tsd ST 24MHz Each Set state serves to set ADC control signals for current channel through corresponding analog registers To select differential input mode SAR_ADC CHCFG MODEL left channel SAR_ADC CHCFG MODER right channel or SAR_ADC CHCFG MODEM ...

Page 163: ...APCFG CTML and SAR_ADC CAPCFG CTMH Similarly the length of Capture state for left and right channel is defined as Tcd CTLR 24MHz where CTLR is configured in the analog registers SAR_ADC CAPCFG CTLRL and SAR_ADC CAPCFG CTLRH The status flag SAR_ADC DATM VLD is set at the end of Capture state to indicate the ADC data is valid and this flag bit will be cleared automatically The 15 bit ADC output data...

Page 164: ...TM 3 ST 2 CTLR 24MHz 500 24MHz 20 83µs Fs Sampling frequency Fs 1 Ttd 24MHz 500 48kHz Select differential input SAR_ADC CHCFG MODEL 1 differential input SAR_ADC CHCFG MODER 1 differential input SAR_ADC CHCFG MODEM 1 differential input Set input channel SAR_ADC CHL_INPUT 0x12 Select B0 and B1 as positive input and negative input SAR_ADC CHR_INPUT 0x34 Select B2 and B3 as positive input and negative...

Page 165: ...n Address 0x00e7 Reset 0x00 7 6 5 4 3 2 1 0 SAR_ADC VREF_CTRL RSVD VREFM VREFR VREFL rw 0 rw 0 rw 0 rw 0 5 4 VREFM VREF Misc channel selection 00 Select VREF 0 6V 01 Select VREF 0 9V 10 Select VREF 1 2V 11 Not used 3 2 VREFR VREF right channel selection 00 Select VREF 0 6V 01 Select VREF 0 9V 10 Select VREF 1 2V 11 Not used 1 0 VREFL VREF left channel selection 00 Select VREF 0 6V 01 Select VREF 0...

Page 166: ...hannel 0 Select no input channel 1 Select Port B Pin 0 as input 2 Select Port B Pin 1 as input 3 Select Port B Pin 2 as input 4 Select Port B Pin 3 as input 5 Select Port B Pin 4 as input 6 Select Port B Pin 5 as input 7 Select Port B Pin 6 as input 8 Select Port B Pin 7 as input 9 Select Port C Pin 4 as input 10 Select Port C Pin 5 as input 11 Select pga_p Pin 0 PGA left channel positive output 1...

Page 167: ...rt B Pin 1 as input 3 Select Port B Pin 2 as input 4 Select Port B Pin 3 as input 5 Select Port B Pin 4 as input 6 Select Port B Pin 5 as input 7 Select Port B Pin 6 as input 8 Select Port B Pin 7 as input 9 Select Port C Pin 4 as input 10 Select Port C Pin 5 as input 11 Select pga_n Pin 0 PGA left channel negative output 12 Select pga_n Pin 1 PGA right channel negative output 13 Select tempsensor...

Page 168: ...hannel 0 Select no input channel 1 Select Port B Pin 0 as input 2 Select Port B Pin 1 as input 3 Select Port B Pin 2 as input 4 Select Port B Pin 3 as input 5 Select Port B Pin 4 as input 6 Select Port B Pin 5 as input 7 Select Port B Pin 6 as input 8 Select Port B Pin 7 as input 9 Select Port C Pin 4 as input 10 Select Port C Pin 5 as input 11 Select pga_p Pin 0 PGA left channel positive output 1...

Page 169: ...rt B Pin 1 as input 3 Select Port B Pin 2 as input 4 Select Port B Pin 3 as input 5 Select Port B Pin 4 as input 6 Select Port B Pin 5 as input 7 Select Port B Pin 6 as input 8 Select Port B Pin 7 as input 9 Select Port C Pin 4 as input 10 Select Port C Pin 5 as input 11 Select pga_n Pin 0 PGA left channel negative output 12 Select pga_n Pin 1 PGA right channel negative output 13 Select tempsensor...

Page 170: ...channel 0 Select no input channel 1 Select Port B Pin 0 as input 2 Select Port B Pin 1 as input 3 Select Port B Pin 2 as input 4 Select Port B Pin 3 as input 5 Select Port B Pin 4 as input 6 Select Port B Pin 5 as input 7 Select Port B Pin 6 as input 8 Select Port B Pin 7 as input 9 Select Port C Pin 4 as input 10 Select Port C Pin 5 as input 11 Select pga_p Pin 0 PGA left channel positive output ...

Page 171: ... input 11 Select pga_n Pin 0 PGA left channel negative output 12 Select pga_n Pin 1 PGA right channel negative output 13 Select tempsensor_n temperature sensor negative output 14 Select GND 15 Select GND 14 2 5 SAR_ADC CHCFG SAR General Channel Configuration Address 0x00eb Reset 0x0333 7 6 5 4 3 2 1 0 SAR_ADC CHCFG 1 RSVD MODEM MODER MODEL RSVD RESM rw 0 rw 0 rw 0 rw 0 rw 0 rw 3 SAR_ADC CHCFG 0 RS...

Page 172: ...resolution 01 Select 10 bit resolution 10 Select 12 bit resolution 11 Select 14 bit resolution 5 4 RESR Right channel resolution selection 00 Select 8 bit resolution 01 Select 10 bit resolution 10 Select 12 bit resolution 11 Select 14 bit resolution 1 0 RESL Left channel resolution selection 00 Select 8 bit resolution 01 Select 10 bit resolution 10 Select 12 bit resolution 11 Select 14 bit resolut...

Page 173: ...3 cycles sampling time 1 6 cycles sampling time 2 9 cycles sampling time 3 12 cycles sampling time 4 15 cycles sampling time 5 18 cycles sampling time 6 21 cycles sampling time 7 24 cycles sampling time 8 27 cycles sampling time 9 30 cycles sampling time 10 33 cycles sampling time 11 36 cycles sampling time 12 39 cycles sampling time 13 42 cycles sampling time 14 45 cycles sampling time 15 48 cycl...

Page 174: ...h byte 19 16 ST State length of 24M clock cycle number that is occupied by the Set state for left right and Misc channel 15 8 CTLRL State length of 24M clock cycle number that is occupied by the Capture state for left and right channel low byte 7 0 CTML State length of 24M clock cycle number that is occupied by the Capture state for Misc channel low byte 14 2 8 SAR_ADC CHEN SAR Channel Enable Cont...

Page 175: ...dress 0x00f7 Reset 0x00 7 6 5 4 3 2 1 0 SAR_ADC DATM 1 VLD DAT ro 0 ro 0 SAR_ADC DATM 0 DAT ro 0 15 VLD ADC data status indication This bit is set by hardware when the data of the last ADC conversion has been written to the DAT field It is cleared at the beginning of every new conversion 0 Data in field DAT is not valid 1 Data in field DAT is valid 14 0 DAT Data from Misc channel 14 2 11 SAR_ADC A...

Page 176: ...ls from specific AMIC pins before ADC sampling Figure 33 Block Diagram of PGA Notes Vip 0 Vin 0 Positive Negative input of PGA left channel Vop 0 Von 0 Positive Negative output of PGA left channel Vip 1 Vin 1 Positive Negative input of PGA right channel Vop 1 Von 1 Positive Negative output of PGA right channel 15 1 Power on down Both PGA channels are powered down by default To power on the PGA cha...

Page 177: ...dB 1b 0 default or 38dB 1b 1 while register FGAIN serves to set gain for the post amplifier as 10dB 0x0 default 14dB 0x30 with step of 0 5dB The total PGA gain should be the sum of the two gain values Refer to section Manual Regulation in Analog Mode for details Manual mode 2 If manual mode 2 is enabled the PGA gain will be automatically adjusted to the pre configured target gain value with the pr...

Page 178: ... INLN Left channel negative input source selection Gate off all input with pga_pd_l 00 Select Port C Pin 1 as input 01 Select no input 10 Select no input 11 Select no input 1 0 INLP Left channel positive input source selection Gate off all input with pga_pd_l 00 Select Port C Pin 0 as input 01 Select no input 10 Select no input 11 Select no input ...

Page 179: ...difference of the two way VBE signals VBE is determined by the real time temperature T as shown below VBE 130mV 0 51mV C T 40 C 130mV 0 51mV C T 40 C In this formula 130mV indicates the value of VBE at the temperature of 40 C To detect the temperature the positive and negative output of the temperature sensor should be enabled as the input channels of the SAR ADC The ADC will convert the two way V...

Page 180: ...e the low power comparator outputs high or low level accordingly Figure 35 Block Diagram of Low Power Comparator 17 1 Power on down The low power comparator is powered down by default The bit LPCPD in the analog register SCTL PDC1 serves to control the power state of the low power comparator By clearing this bit the comparator is powered on by setting this bit to 1b 1 the comparator is powered dow...

Page 181: ... The analog register LPC CFG0 VSCAL serves to select one of the four scaling options 25 50 75 and 100 17 5 Low Power Comparator Output The low power comparator output is determined by the comparison result of the value of input voltage scaling and reference voltage input The comparison principle is shown as below If the value of input voltage scaling is larger than reference voltage input the outp...

Page 182: ... mode 010 Select 921mV as reference voltage in normal mode Select 913mV as reference voltage in low power mode 011 Select 870mV as reference voltage in normal mode Select 862mV as reference voltage in low power mode 100 Select 819mV as reference voltage in normal mode Select 810mV as reference voltage in low power mode 111 Select AVDD3 as reference voltage in normal and low power mode Others Reser...

Page 183: ...ly 3 For encryption method write registers AES DAT for four times to set the 128 bit plaintext After encryption the 128 bit ciphertext can be obtained by reading AES DAT for four times 4 For decryption method write registers AES DAT for four times to set the 128 bit ciphertext After decryption the 128 bit plaintext can be obtained by reading AES DAT for four times 5 AES CTRL IDRDY will be cleared ...

Page 184: ...bles CCM mode for further AES processing 2 ODRDY Signals the processing of the data in the output buffer 0 Output data needed 1 Output data ready 1 IDRDY Signals the processing of the data in the input buffer 0 Input data needed 1 Input data ready 0 SEL Selection to decrypt or encrypt current data 0 Selects encryption of the data 1 Selects decryption of the data 18 4 2 AES DAT AES Data Address 0x0...

Page 185: ... 6 5 4 3 2 1 0 AES KEY 15 KEY15 rw 0 AES KEY 14 KEY14 rw 0 AES KEY 13 KEY13 rw 0 AES KEY 12 KEY12 rw 0 AES KEY 11 KEY11 rw 0 AES KEY 10 KEY10 rw 0 AES KEY 9 KEY9 rw 0 AES KEY 8 KEY8 rw 0 AES KEY 7 KEY7 rw 0 AES KEY 6 KEY6 rw 0 AES KEY 5 KEY5 rw 0 AES KEY 4 KEY4 rw 0 AES KEY 3 KEY3 rw 0 AES KEY 2 KEY2 rw 0 AES KEY 1 KEY1 rw 0 AES KEY 0 KEY0 rw 0 ...

Page 186: ...Bluetooth 5 Low Energy and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 186 of 206 Apr 21 21 7 0 15 8 23 16 31 24 39 32 47 40 55 48 63 56 71 64 79 72 87 80 95 88 103 96 111 104 119 112 127 120 KEYx AES Key Data AES Key Data buffer to corresponding byte 128 bit key ...

Page 187: ...Bluetooth LE mode 2Mbps enhancement Bluetooth LE mode 125kbps Bluetooth LE long range mode S8 500kbps Bluetooth LE long range mode S2 IEEE 802 15 4 standard compliant 250kbps mode and Proprietary 1Mbps 2Mbps 250kbps and 500kbps mode The internal PA can deliver a maximum 10dBm output power avoiding the need for an external RF PA Figure 36 Block Diagram of RF Transceiver 19 2 Baseband The baseband i...

Page 188: ...ts TERM2 3 bits MSB Packet format in 250kbps 802 15 4 mode is shown as Table 19 Table 19 Packet Format in 802 15 4 Mode LSB Preamble 4 octets SFD 1 octet Frame length 1 octet PSDU Variable 0 127 octets CRC 2 octets MSB PHR PHY payload Packet format in 2 4GHz Proprietary mode is shown as Table 20 Table 20 Packet Format in Proprietary Mode LSB Preamble 8 bits Address code configurable 3 5 bytes Pack...

Page 189: ...Maximum Units VDD Supply Voltage All AVDD DVDD and VDD_IO pins must have the same voltage 0 3 3 6 V VIn Voltage on Input Pin 0 3 VDD 0 3 V VOut Output Voltage 0 VDD V TStr Storage Temperature Range 65 150 C TSld Soldering Temperature 260 C CAUTION Stresses above those listed in Table 21 can cause permanent damage to the device This is a stress only rating and operation of the device at these or an...

Page 190: ...out SRAM retention 0 4 uA Table 24 AC Characteristics VDD 3 3V TA 25 C Symbol Parameter Conditions Minimum Typical Maximum Units Digital Inputs Outputs VIH Input High Voltage 0 7VDD VDD V VIL Input Low Voltage VSS 0 3VDD V VOH Output High Voltage 0 9VDD VDD V VOL Output Low Voltage VSS 0 1VDD V RF Parameters RF Frequency Range Programmable in 1MHz step 2380 2500 MHz Data Rate Bluetooth LE 2 4G Pro...

Page 191: ...qual Modulation Interference Wanted signal at 67dBm 42 dB Image Rejection Wanted signal at 67dBm 37 dB TX Performance Output Power Maximum Setting 10 12 dBm Output power Minimum Setting 45 dBm Programmable Output Power range 55 dB Modulation 20dB Bandwidth 1 4 MHz a For actual sensitivity level of Bluetooth LE 1Mbps mode see Bluetooth 5 specification Table 26 Bluetooth LE 2 Mbps Mode Symbol Parame...

Page 192: ...rameter Conditions Minimum Typical Maximum Units RX Performance c 250kHz Deviation 500kbps Sensitivity 99 dBm Frequency Offset Tolerance 150 50 kHz Co channel Rejection Wanted signal at 67dBm 1 dB 1 1 MHz offset In band Blocking Rejection Equal Modulation Interference Wanted signal at 67dBm 34 36 dB 2 2 MHz offset 42 42 dB 3MHz offset 42 dB Image Rejection Wanted signal at 67dBm 42 dB TX Performan...

Page 193: ...et Tolerance 150 50 kHz Co channel Rejection Wanted signal at 67dBm 3 dB 1 1 MHz offset In band Blocking Rejection Equal Modulation Interference Wanted signal at 67dBm 32 34 dB 2 2 MHz offset 42 42 dB 3MHz offset 42 dB Image Rejection Wanted signal at 67dBm 42 dB TX Performance Output Power Maximum Setting 10 12 dBm Output Power Minimum Setting 45 dBm Programmable Output Power Range 55 dB Modulati...

Page 194: ...tput 2 Tx Performance Output Power Maximum Setting 10 12 dBm Output power Minimum Setting 45 dBm Programmable Output 55 dB Power Range Modulation 20dB Bandwidth 2 7 MHz e For actual sensitivity level of IEEE802 15 4 mode see 802 15 4 specification Symbol Parameter Conditions Minimum Typical Maximum Units Module Internal 24MHz Crystal fNOM Nominal Frequency 24 MHz fTOL Frequency Tolerance 20 20 ppm...

Page 195: ... bits FS Sampling Frequency 200 ksps 20 4 SPI Characteristics Table 30 SPI Characteristics over process voltage 1 9 3 6V and TA 40 to 85 C Symbol Parameter Conditions Minimum Typical Maximum Units FCK CK Frequency Slave 4 MHz CK Duty Cycle Clock Master 50 DI Setup Time Slave 30 ns Master 90 ns DI Hold Time Slave 10 ns Master 90 ns CK Low to DO Valid Time Slave 30 ns Master 120 ns CN Setup Time Mas...

Page 196: ...A and SCL Signals 300 300 ns THD STA START Condition Hold Time 4 0 6 µs THD DAT Data Hold Time 0 3 45 0 9 µs TSU DAT Data Setup Time 250 100 ns TSU STO STOP Condition Setup Time 4 0 6 µs 20 6 Flash Characteristics Table 32 Flash Characteristics TA 40 to 85 C Symbol Parameter Conditions Minimum Typical Maximum Units Retention Period 20 Year Number of Erase Cycles 100k Cycle VDD for Programming This...

Page 197: ...onal Use Conditions 21 2 1 North America FCC The module must not be operated at power levels above 10 0dBm Host devices that need higher output power may not be marketed without prior re certification 21 2 2 Europe RED The module must not be operated at power levels above 8 4dBm Host devices that need higher output power may not be marketed in regions covered by RED regulation without prior re cer...

Page 198: ...ayout Guidelie Host PCB Antenna keep out area No copper or components allowed 3 3 mm 6 1 mm RYZ012A1 21 3 2 RZY012B1 Do not place any metal in the keep out area no traces planes components batteries screws Ensure the module is properly connected to ground e g ground plane Ensure the antenna connection trace is 50Ohms matched to achieve proper antenna performance ...

Page 199: ...5 Low Energy and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 199 of 206 Apr 21 21 Figure 38 RYZ012B1 Layout Guideline Host PCB Keep out area No copper or metallic objects here RYZ012B1 a b c d 0 65 0 75 0 25 0 8 Dimension mm b b e b a c d e 1 1 Antenna connector 50Ω trace ...

Page 200: ... 39 AWR TXLine Tool for Antenna Trace Impedance Calculation 21 4 Antennas 21 4 1 RYZ012A1 The RYZ012A1 has an integrated antenna The host integrator should follow the instructions from section 21 to ensure best antenna performance 21 4 2 RYZ012B1 The RYZ012B1 doesn t have an own antenna but comes with an antenna pad instead The antenna must be provided by the host device Please strictly follow the...

Page 201: ...statement cannot be included on the host device label this statement must be included in the users manual of the host device 21 6 2 ISED Canada Host devices integrating the RYZ012 should indicate the use of this module on a label on the host device by the following statement In addition the host device should include the following text on the label if possible Contains FCC ID COR RYZ012X1 This dev...

Page 202: ...module on a label on the host device by the following statement Translation This equipment contains specified radio equipment that has been certified to the Technical Regulation Conformity Certification under the Radio Law 21 7 Information on test modes and additional testing requirements The module can provide RF signals required for additional regulatory testing through a dedicated firmware This...

Page 203: ...couraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Caution Any changes or modification no...

Page 204: ...and 802 15 4 R15UH0002EU0103 Rev 1 03 Page 204 of 206 Apr 21 21 23 Package Outline Drawings Table 33 Module Dimensions In mm Min Nom Max D 11 85 12 00 12 15 E 11 85 12 00 12 15 b 0 7 0 8 0 9 b2 0 96 L 0 9 1 00 1 1 e 1 4 c 0 75 c1 2 5 c2 4 6 c3 1 1 H 2 16 2 31 2 46 t 0 71 0 81 0 91 ...

Page 205: ...Recommended Soldering Profile It is important to ensure this temperature profile is measured at the sensor itself Measuring the profile at a larger component with a higher thermal mass results in the temperature at the small sensor measuring higher than expected For manual soldering the contact time must be limited to 5 seconds with a maximum iron temperature of 350 C It is strongly recommended th...

Page 206: ...le needing external antenna 3 Tape Reel 40 C to 85 C RYZ012A100FZ00 BD0 Module with internal antenna 3 Tray 40 C to 85 C 26 Marking Diagram 27 Revision History Revision Date Description of Change Oct 09 2020 Initial release Jan 13 2021 Fixed several typos Feb 19 2021 Fixed typos and usage of Bluetooth and Bluetoot Low Energy terms Apr 9 2021 Specified Tape Reel for Shipping Packaging Removed refer...

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