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RX Family

Hardware Design Guide

R01AN1411EJ0110 Rev.1.10

Page 30 of 32

Oct.26.21

+3.3 V

+3.3 V

Refer to Figure 2.8 for
the purpose of the slits.

Figure 3.7 Example Board Wiring Pattern (Third Layer Wiring Pattern)

GND

GND

Analog

GND

Figure 3.8 Example Board Wiring Pattern (Fourth Layer Wiring Pattern)

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Summary of Contents for RX Family

Page 1: ... 2 Component Layout 3 1 3 Layer Structure 5 2 Board Design 7 2 1 Power Supply Pins 7 2 2 VCL Pin 9 2 2 1 Two Layer Board 11 2 2 2 Board With Four or More Layers 13 2 3 Reset Pin 14 2 4 Clock I O Pins 16 2 5 Analog Input Pins 21 2 6 Signal Pins with Large Current Flows 23 2 7 Signal Pins with Rapid Level Changes 23 3 Board Wiring Pattern Examples 24 3 1 Example Two Layer Board Wiring Pattern 24 3 2...

Page 2: ...lock Diagram Figure 1 1 shows a block diagram of the board configuration used in the design example RX Family Main crystal oscillator Sub crystal oscillator Power supply circuit Reset circuit 3 3 V Reset signal Analog input Analog signal Main clock Subclock External power supply 5 V Figure 1 1 Block Diagram ...

Page 3: ...and R5 are usually unnecessary In Figure 1 2 no feedback resistors are mounted If the oscillator manufacturer stipulates that external feedback resistors or damping resistors should be added mount them according to the manufacturer s specification In some cases 0 Ω damping resistors R3 and R5 or wiring pattern connection can be used Analog input Subclock Reset circuit DC jack Power supply circuit ...

Page 4: ...RX Family Hardware Design Guide R01AN1411EJ0110 Rev 1 10 Page 4 of 32 Oct 26 21 Figure 1 3 Component Layout Back Side ...

Page 5: ...tern GND signal and analog GND First layer wiring pattern Power supply signal and analog power supply Fourth layer wiring pattern Signal and analog GND Third layer wiring pattern Solid power layer Second layer wiring pattern Solid GND layer First layer wiring pattern Signal and analog power supply Two layer board Four layer board Figure 1 4 Layer Structure Examples ...

Page 6: ...ock Subclock Analog GND Analog power supply Single point connection to analog GND Red 3 3 V route Green GND route Arrange the paths of the power and GND traces from the power supply circuit to VCC VSS as a pair A typical route is shown as an example Also in this example the paths on the first and second layers are superimposed on one another to form a pair Figure 1 5 Example Wiring Pattern for Two...

Page 7: ...pply wiring pattern Good power supply wiring pattern C Capacitor Through hole Wiring trace VSS VCC VSS VCC RX Family RX Family Connections between pins capacitor and through hole are as short as possible Not appropriate because the power supply pins are connected to GND without an intervening capacitor Appropriate because the power supply pins are connected to GND via a capacitor Digital GND Digit...

Page 8: ...uit configuration and Figure 2 3 shows an example power supply pin wiring pattern VCC VSS RX Family MCU Connection to power supply Figure 2 2 Example Power Supply Pin Circuit Configuration 3 3 V GND Bypass capacitor Make connection to through hole via a capacitor VSS pin VCC pin Figure 2 3 Example Power Supply Pin Wiring Pattern ...

Page 9: ...acitor and possibly causing noise from the VCC pin When the wiring length between the VCL pin and capacitor is longer than 8 mm the wiring pattern should be designed so that the parasitic resistance is less than 1 Ω Figure 2 4 shows a formula for calculating the parasitic resistance w l t Wiring on printed circuit board Parasitic resistance R 2pfL Ω 1 Ω R l σwt Ω f 20 MHz internal fluctuation in M...

Page 10: ...32 Oct 26 21 Figure 2 5 shows an example circuit configuration for the VCL pin VCL VSS RX Family MCU Refer to the user s manual of the device used regarding the rated capacitance of the capacitor connected to the VCL pin Figure 2 5 Example VCL Pin Circuit Configuration ...

Page 11: ...ast four through holes Make the GND wiring traces as wide as possible Figure 2 6 shows an example VCL pin wiring pattern on a two layer board C Capacitor VCL VSS C Front side wiring pattern Back side wiring pattern a b a and b 8 mm 4 mm if possible When a and b 8 mm ensure parasitic resistance for a and b is less than 1 Ω Through hole VBAT Layer under VCL is GND Four or more through holes Figure 2...

Page 12: ... 32 Oct 26 21 Figure 2 7 shows an example VCL pin wiring pattern two layer board GND GND Four or more GND through holes Four or more GND through holes VCL capacitor GND under VCL signal VCL pin VBAT pin VSS pin Figure 2 7 Example VCL Pin Wiring Pattern Two Layer Board ...

Page 13: ...rn board with four or more layers GND GND Four or more GND through holes Four or more GND through holes VCL capacitor GND under VCL signal Make a slit to allow coupling of the VCL capacitor and VSS pin Make a slit to allow coupling of the subclock GND guard and VSS pin VCL pin VBAT pin VSS pin Figure 2 8 Example VCL Pin Wiring Pattern Board With Four or More Layers ...

Page 14: ...to the reset pin has a shorter width than the specified pulse width a reset condition may be released before the MCU s internal initialization has completed possibly causing program runaway Figure 2 9 shows an example reset pin circuit configuration and Figure 2 10 shows an example reset pin wiring pattern multilayer board RES VSS RX Family MCU Reset IC RNA51957 OUT GND Figure 2 9 Example Reset Pi...

Page 15: ...esign Guide R01AN1411EJ0110 Rev 1 10 Page 15 of 32 Oct 26 21 Figure 2 11 shows an example reset pin wiring pattern RX Family Reset IC Filter circuit Reset signal RES pin VSS pin Figure 2 11 Example Reset Pin Wiring Pattern ...

Page 16: ...ating a crystal oscillator Refer to the application notes below for information on crystal oscillators with low load capacitance low CL crystal oscillators The latest versions and guides to new products can be downloaded from the Renesas Electronics website RX200 Series Design Guide for Sub Clock Circuits R01AN1012EJ RX600 RX700 Series Design Guide for Sub Clock Circuits R01AN1187EJ Board design h...

Page 17: ...s enclosed by the yellow borders which is used for the GND wiring pattern on the back side Also the back side GND wiring traces should be at least 0 1 mm wider than the front side GND wiring traces However there must be no wiring traces on the back side if the board thickness is less than 1 2 mm Strengthen the GND guard between the front side and back side with optimal placement of through holes I...

Page 18: ...ole Front side wiring pattern Resistor Capacitor R XCIN RX Family XCOUT XTAL EXTAL VSS R C C C R R C C The front side GND shielding width should be at least 0 3 mm Through hole for VSS coupling Crystal oscillator Crystal oscillator Figure 2 14 Example Clock I O Pin Wiring Pattern Front Side ...

Page 19: ...iring pattern Through hole Through hole for VSS coupling The back side GND wiring pattern is divided into three islands as indicated by the yellow borders one for each crystal oscillator The wiring pattern also allows for VSS coupling Figure 2 15 Example Clock I O Pin Wiring Pattern Back Side ...

Page 20: ...age 20 of 32 Oct 26 21 Figure 2 16 shows an example clock I O pin wiring pattern GND guard Crystal oscillator Feedback resistor Crystal oscillator Limiting resistor Limiting resistor GND guard XCIN XCOUT XTAL VSS EXTAL Figure 2 16 Example Clock I O Pin Wiring ...

Page 21: ...become distorted possibly reducing A D converter accuracy An external capacitor can be used to reduce noise An external capacitor can also be used to achieve high speed conversion This requires that sufficient electrical charge has accumulated in the external capacitor before conversion starts to reduce the signal source impedance of the input capacitor of the sample and hold circuit Note that if ...

Page 22: ...ly Front side wiring pattern Back side wiring pattern Analog GND shield Analog input The analog signal is shielded by the analog GND wiring trace trace width at least 0 3 mm Analog power supply C C C C Figure 2 18 Example Analog Input Pin Wiring Pattern Figure 2 19 shows an example analog input pin wiring pattern Analog GND guard Analog GND guard Analog input pin Figure 2 19 Example Analog Input P...

Page 23: ...rents flow in these signal lines mutual inductance with parallel wiring traces can cause noise 2 7 Signal Pins with Rapid Level Changes Place signal lines with rapid level changes as far from the oscillators and the wiring traces of the oscillators as possible Do make such signal lines any longer than necessary and ensure they do not run parallel to or across the clock related signal lines or othe...

Page 24: ...ard wiring pattern for an RX Family MCU and Figure 3 2 and Figure 3 3 show the wiring patterns for the first and second layers separately RX Family GND GND GND GND 5 V 3 3 V 3 3 V GND Main clock oscillator Sub clock oscillator Bypass capacitor load capacitance VCL capacitor Analog power supply Analog GND Reset IC RNA51957 Power IC ISL80030 Figure 3 1 Example Board Wiring Pattern Two Layer Board ...

Page 25: ... 10 Page 25 of 32 Oct 26 21 RX Family GND GND 5 V 3 3 V Main clock oscillator Sub clock oscillator GND guard analog GND guard Analog power supply Reset IC RNA51957 Power IC ISL80030 3 3 V Figure 3 2 Example Board Wiring Pattern First Layer Wiring Pattern ...

Page 26: ...RX Family Hardware Design Guide R01AN1411EJ0110 Rev 1 10 Page 26 of 32 Oct 26 21 GND GND GND GND Analog GND 3 3 V Figure 3 3 Example Board Wiring Pattern Second Layer Wiring Pattern ...

Page 27: ...an RX Family MCU and Figure 3 5 Figure 3 6 Figure 3 7 and Figure 3 8 show the wiring patterns for each of the individual layers separately RX Family GND GND GND 5 V Main clock oscillator Sub clock oscillator Bypass capacitor load capacitance VCL capacitor Analog power supply Analog GND GND GND GND Reset IC RNA51957 Power IC ISL80030 Figure 3 4 Example Board Wiring Pattern Four Layer Board ...

Page 28: ...ev 1 10 Page 28 of 32 Oct 26 21 RX Family GND GND 5 V Main clock oscillator Sub clock oscillator Analog power supply GND Reset IC RNA51957 Power IC ISL80030 GND guard Analog GND guard Figure 3 5 Example Board Wiring Pattern First Layer Wiring Pattern ...

Page 29: ...amily Hardware Design Guide R01AN1411EJ0110 Rev 1 10 Page 29 of 32 Oct 26 21 GND GND GND Refer to Figure 2 8 for the purpose of the slits Figure 3 6 Example Board Wiring Pattern Second Layer Wiring Pattern ...

Page 30: ... Rev 1 10 Page 30 of 32 Oct 26 21 3 3 V 3 3 V Refer to Figure 2 8 for the purpose of the slits Figure 3 7 Example Board Wiring Pattern Third Layer Wiring Pattern GND GND Analog GND Figure 3 8 Example Board Wiring Pattern Fourth Layer Wiring Pattern ...

Page 31: ... downloaded from the Renesas Electronics website RX610 Group Notes on Analog Power Supply Printed Circuit Board Patterns R01AN0271EJ RX62N Group RX621 Group Notes on Analog Power Supply Printed Circuit Board Patterns R01AN0269EJ RX62T Group Notes on Analog Power Supply Printed Circuit Board Patterns R01AN0638EJ RX200 Series Design Guide for Sub Clock Circuits R01AN1012EJ RX600 RX700 Series Design ...

Page 32: ...ct 26 2021 2 New Section 1 added subsequent section and figure numbers changed accordingly 4 Section 1 2 1 deleted 7 Section 2 items modified VCL capacitor wiring limitations modified 10 Figure 2 5 note on rated capacitance of VCL capacitor added 14 16 21 GND guard wiring width and spacing conditions added 16 Figure 2 12 note on load capacitance and VSS pin coupling added 24 to 30 Example single l...

Page 33: ...put signal during power off state as described in your product documentation 4 Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of the ...

Page 34: ...D ALL WARRANTIES EXPRESS OR IMPLIED WITH RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 8 When using Renesas Electronics products refer to the latest product information data sheets user s manuals application notes General Notes for Handling and Using Semiconduc...

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