CHAPTER 14 SERIAL ARRAY UNIT
Page 340 of 920
14.3.6
Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 14 - 11 Format of Serial flag clear trigger register mn (SIRmn)
Note
The SIR03 and SIR13 registers only.
Caution
Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR02, SIR10 to SIR12 register) to “0”.
Remark
When the SIRmn register is read, 0000H is always read.
Address: F010CH, F010DH (SIR02), F010EH, F010FH (SIR03),
After reset: 0000H
F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
FEC
Tmn
PEC
Tmn
OVC
Tmn
Clear trigger of framing error of channel n
0
Not cleared
1
Clears the FEFmn bit of the SSRmn register to 0.
Clear trigger of parity error flag of channel n
0
Not cleared
1
Clears the PEFmn bit of the SSRmn register to 0.
Clear trigger of overrun error flag of channel n
0
Not cleared
1
Clears the OVFmn bit of the SSRmn register to 0.
Summary of Contents for RL78/G1H
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