Functional Overview
2.3 Memory
Rev.1.0 Feb 06. 2007
2-6
REJ10J0916-0100
2
Figure2.3.2 shows an example of SDRAM single read/write timing for operation with the SH7086 Bus clock at
40MHz.
CKIO
CKE
CS3
RASL
CASL
RDWR
DQMUU-LL
MA0-9,11
MA10
BA0-1
D0-31
tcyc
(25ns)
ACT
DESEL
DESEL
READA
DESEL
DESEL
DESEL
DESEL
DESEL
ACT
DESEL
DESEL
WRITA
DESEL
DESEL
DESEL
DESEL
tSI
tSI
Tr
Trw
Trw
Tc1
Tcw
Td1
Tde
Tap1
Tap2
tCSD
tRASD
SDRAM SINGLE READ
Tr
Trw1
Trw2
Tc1
Trwl1
Trwl2
Tap1
Tap2
SDRAM SINGLE WRITE
tHI
tCSD
tSI
tCSD
tHI
tCSD
tHI
tRASD
tRC
tRCD
tRAS
tSI
tRASD
tHI
tRASD
tRCD
tRAS
tRC
tSI
tCASD
tHI
tCASD
tSI
tCASD
tHI
tCASD
tSI
tRWD
tHI
tRWD
tDQMD
Data
tAD1
tAD1
tAD1
tAC
tRDS2
tRDH2
tOH
tAD1
tSI
tHI
tAD1
tSI
tHI
tDQMD
tDQMD
tSI
tHI
tDQMD
tAD1
tAD1
tSI
tHI
tAD1
tWDD2
tSI
tHI
tWDH2
Figure2.3.2 Example of SDRAM Single Read/Write Timing
Summary of Contents for Renasas Single-Chip Microcomputer SH7086
Page 7: ...1 1 Chapter1 Overview Chapter1 Overview...
Page 19: ...2 1 Chapter2 Functional Overview Chapter2 Functional Overview...
Page 37: ...3 1 Chapter 3 Operational Specifications Chapter 3 Operational Specifications...
Page 59: ...Appendix M3A HS86 SCHEMATICS A 1...
Page 60: ...This is a blank page A 2...
Page 68: ...This is a blank page...