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Renesas R-Car V3M, Manual

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Renesas R-Car V3M Manual Download Page 26

R-CAR V3M Starter Kit 

 

 

R12UT0003ED0230  Rev 2.30 

 

Page 26 of 54 

January 24, 2019 

 

Under development

 

Preliminary document 
Specifications in this document are tentative and subject to change.

 

5. Flash Memory Selection 

The  system  booting  can  be  done  from  three  different  sources.  The  first  one  is  a  Hyper-Flash  memory,  the  second  is  a 
standard on-board QSPI memory and the last option is through the CoM-Express connector. The last method offers the 
possibility to boot from an external QSPI memory placed on a daughter board.  

The multiplexers are driven by the CPLD. The CPLD contains a register where the SoC Mode is configured. This register 
can be modified either with the GUI or with the switch SW4.    

5.1 

Multiplexing drawing 

The Figure 16 illustrates the flash memories multiplexing schema. The V3M SoC has two different QSPI interfaces which 
are connected to the three different sources. The CPLD determinates which QSPI path is connected to the SoC. Note that 
just one or two QSPI customer memories may be installed in a daughter board if the CoM-Express connector is used.  

 

Figure 16. Flash memories multiplexing drawing.  

5.2 

Flash Memory Selection (via CPLD/GUI) 

The user can select which QSPI device will be selected by clicking on the tab “On-board peripheral configuration”. Then 
select one option on the “QSPI device” checkbox as shown in the Figure 17.  

When  the  desired  configuration  is  chosen,  click  on  Write  CPLD  (volatile)  or  Write  CPLD  (non-volatile).  If  the  Write 
(volatile) button is pressed, the changes will remain active until the board is powered off. If permanent changes must be 
applied then click on Write CPLD (non-volatile) button. 

 

Hyperflash

S26KS512S

On Board

QSPI

CoM-Express

R-Car V3M

QSPI0

CPLD

PC

MD[4:1]

SW4.8

QSPI1

QSPI0

QSPI1

QSPI0

QSPI1

External QSPI 

Memories

V3M Starter Kit

GPIOx

Summary of Contents for R-Car V3M

Page 1: ...ed in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice...

Page 2: ...High Quality Transportation equipment automobiles trains ships etc traffic control traffic lights large scale communication equipment key financial terminal systems safety control equipment etc Renesa...

Page 3: ...ing such weapons 2 any purpose relating to the development design manufacture or use of conventional weapons or 3 any other purpose of disturbing international peace and security and you shall not sel...

Page 4: ...ss is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches t...

Page 5: ...r attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history...

Page 6: ...of 54 January 24 2019 Under development Preliminary document Specifications in this document are tentative and subject to change 2 Notation of Numbers and Symbols The symbol suffixed to the pin or si...

Page 7: ...l Peripheral Interface QSPI Quad Serial Peripheral Interface CoM Express Computer on Module Express HSSTP High Speed Serial Trace Probe for High Speed Debugging LVDS Low voltage differential signaling...

Page 8: ...2 Configuration tool overview 23 4 3 Volatile Non volatile 24 4 4 Terminal blocking virtual COM ports 24 4 5 SCIF disabled by hardware 24 5 Flash Memory Selection 26 5 1 Multiplexing drawing 26 5 2 Fl...

Page 9: ...loading Mini Monitor 42 15 Procedure for flashing on board QSPI and Hyper Flash memories 44 15 1 Hardware set up 44 15 2 QSPI Flash Erasing 44 15 3 Writing the boot loader IPL to the QSPI sector 1 45...

Page 10: ...de settings by register or by DIP SW4 selection 27 Figure 19 SoC Mode interface 27 Figure 20 Write CPLD 28 Figure 21 eMMC block diagram 29 Figure 22 LVDS path multiplexing 30 Figure 23 LVDS and HDMI s...

Page 11: ...d subject to change Tables Table 1 Board functions 12 Table 2 Order codes 14 Table 3 Fan connector pinout 16 Table 4 SoC mode 18 Table 5 Connectors 19 Table 6 JTAG Connector pinout 20 Table 7 Switch d...

Page 12: ...cations based on the SoC R CAR V3M from Renesas Electronics Table 1 Board functions Board Function Item Description Note CPU ARM CA53 ARMv8 800 MHz dual core with NEON VFPv4 L1 I D 32K 32K L2 512K ARM...

Page 13: ...r Raw max 100 MHz shared with many other functions Interfaces EthAVB PHY RJ45 connector 100 1000 Alternatively to on board PHY RGMII V1 3 interface 2 5V SCIF 1 channel via Mini USB B via FT232 USB to...

Page 14: ...er switch The SW1 and SW2 have no function Figure 3 Power connector definition 1 3 Order codes Table 2 Order codes Boards Order Codes V3M Starter Kit SoC silicon version 1 0 Y ASK RCAR V3M WS10 V3M St...

Page 15: ...ransmitter ADV7511 HSSTP CN1 HDMI TypeA CN2 FAN CN4 POWER CN5 Reserved CN7 JTAG CN6 MODE SW4 DIP SWITCH 8pos User SW SW5 DIP SWITCH 4pos LED6 LED7 LED8 Symplified block diagram MODE_PINS VDDQ_VIN01 VD...

Page 16: ...cument are tentative and subject to change 1 6 Board releases DS Design Sample main test coverage ES Engineering Sample Function test coverage 80 CS Customer sample Functional test coverage 100 pass M...

Page 17: ...lable on the board The rest of the bits have a default value The preset values are shown in the Table 4 It is possible to write the CPLD register via proprietary CPLD interface or from PC with the GUI...

Page 18: ...4 Boot device selection 3 L H ON MD5 SW4 5 Secure authorization Enabled Disabled OFF MD7 SW4 6 Master boot processor A53 CPU0 CR7 OFF MD8 Databus width of Area 0 space 8 bit 16 bit LOW MD9 EXTAL XTAL...

Page 19: ...r Type Function CN1 ERF8 020 05 0 L DV L K TR HSSTP Connector CN2 HMDI Type A HDMI Output CN3 TYCO ELECTRONICS 3 5353652 6 COM Express Interface CN4 Header 3 way Fan Connector CN5 PJ 063AH Power Input...

Page 20: ...8V 2 VSUPPLY I 1 8V Not connected 3 TRST I 1 8V 4 GND 0V 5 TDI I 1 8V 6 GND 0V 7 TMS I 1 8V 8 GND 0V 9 TCK I 1 8V 10 GND 0V 11 N C O 1 8V 12 GND 0V 13 TDO O 1 8V 14 GND 0V 15 PRESET I O 1 8V Open Drai...

Page 21: ...s document are tentative and subject to change 3 4 LEDs Figure 10 Top view of the board LEDs position Table 8 LEDs description LED Color Function LED1 Red Power LED 3 3V LED2 Red Power LED 5 0V LED3 Y...

Page 22: ...MC memory depend on the batch Minimum size is 8 GiB and maximum 32 GiB Table 9 List of components Renesas V3M PMIC CPLD RGB HDMI USB Converter HyperFlash QSPI Flash 2x DDR3 RAM LVDS to RGB CPLD PHY eM...

Page 23: ...r Figure 13 if the corresponding USB Serial Port COMx is recognized Otherwise install the driver available on the FTDI web page and try again Figure 13 Device manager view Check for COMx ports You can...

Page 24: ...ings are set as volatile these are written in the CPLD registers and are only effective until new power cycle When the settings are set as non volatile these are written in the internal Flash memory o...

Page 25: ...r Kit R12UT0003ED0230 Rev 2 30 Page 25 of 54 January 24 2019 Under development Preliminary document Specifications in this document are tentative and subject to change Figure 15 Routing SCIF0 to CoM E...

Page 26: ...oC has two different QSPI interfaces which are connected to the three different sources The CPLD determinates which QSPI path is connected to the SoC Note that just one or two QSPI customer memories m...

Page 27: ...click on the tab SOC mode configuration The MODE setting checkbox allows to select between the SW4 or CPLD register as a configuration source as shown in the Figure 18 Click on set by this register a...

Page 28: ...ious section the boot mode can be also configured either with the switch SW4 or with the CPLD The SW4 switch is directly connected to the CPLD and modify the SoC mode register bits MD 1 4 Table 10 Boo...

Page 29: ...bject to change 5 5 eMMC memory The V3M Starter Kit includes an on board eMMC memory for mass storage Additionally is possible to place an eMMC memory in a Daughter board Figure 21 shows the eMMC rout...

Page 30: ...lexers The first one multiplex the LVDS signals to the CoM Express connector or to a second multiplexer The second multiplex to the HSSTP connector or to a LVDS RGB and RGB HDMI converter The HDMI int...

Page 31: ...12UT0003ED0230 Rev 2 30 Page 31 of 54 January 24 2019 Under development Preliminary document Specifications in this document are tentative and subject to change Figure 23 LVDS and HDMI selection using...

Page 32: ...4 TDI I 1 8V 15 HSSTP_CH0_N O HSSTP 16 TDO O 1 8V 17 GND Power 0V 18 GND Power 0V 19 HSSTP_CLK_P O HSSTP 20 PRESET I O Open Drain 1 8V 21 HSSTP_CLK_N O HSSTP 22 NC 23 GND Power 0V 24 GND Power 0V 25 H...

Page 33: ...entative and subject to change 8 Ethernet 8 1 Multiplexing drawing As shown in Figure 24 the RGMII interface can be multiplexed to the PHY and RJ45 connector or to a daughter board via CoM Express con...

Page 34: ...are LEDs 9 1 LED 6 LED 7 LED 8 switching via CPLD The Starter Kit contains three user LEDs LED 6 LED 7 and LED 8 These can be mapped to the SoC GPIOs GP1_21 GP1_22 and GP1_23 This feature can be confi...

Page 35: ...IPSW 10 1 Drawing of configuration Figure 27 SW5 drawing of configuration The DIPSW5 is connected to the GP1_21 GP1_22 GP1_23 and GP1_24 through a tristate buffer When the buffer is enabled the GPIOs...

Page 36: ...tions in this document are tentative and subject to change 10 2 SW5 available depending on CPLD The SW5 can be also mapped to the corresponding SoC GPIOs This can be do with the DIPW5 checkbox availab...

Page 37: ...This should be considered when using the V3M Starter Kit to provide proper operation and avoid possible device damages on daughter boards connected to the CoM Express connector 11 2 Drawing of configu...

Page 38: ...ue to the 3 3V power deliver delay between 1 8V and 3 3V Figure 31 VDDQ_VIN01 voltage at start up when set to 3 3V 11 4 Power settings configuration The VDDQ_DU and VDDQ_VIN01 settings can be configur...

Page 39: ...generates a controlled reset output which is applied to the SoC Note that the reset coming from SW3 PC and CoM Express connector is debounced The mode pins are latched during reset The CPLD drive the...

Page 40: ...ications 13 1 Overview SCIF0 is routed to the FT232 USB to UART converter and CN3 CoM Express connector in parallel When the SCIF0 is used on CoM Express connector the CPLD held the FT232 in reset sta...

Page 41: ...2R driver may take several seconds Execute the V3M Starter Kit Configuration Tool In MODE setting select Set by this register In Boot from MD4 3 2 1 select SCIF0 Press Write CPLD volatile or Write CPL...

Page 42: ...is to send the code to be executed e g the Mini Monitor terminal program to the System RAM 14 3 Uploading Mini Monitor To copy the Mini Monitor program into the System RAM we need to send the correspo...

Page 43: ...V3M Starter Kit R12UT0003ED0230 Rev 2 30 Page 43 of 54 January 24 2019 Under development Preliminary document Specifications in this document are tentative and subject to change Figure 40 Command ter...

Page 44: ...iguration tool If you have open a terminal session please close it now Otherwise the communication with the CPLD would not be possible Now start the V3M configuration tool and select the corresponding...

Page 45: ...are tentative and subject to change Figure 42 Mini Mon memory erase This process will takes some time 3 4min Wait until the process is finished Figure 43 Memory erase 15 3 Writing the boot loader IPL...

Page 46: ...and subject to change Figure 45 Program area selection You will be asked to indicate in which area the program should be saved Select the save area and then send the corresponding mot file 15 4 Hyper...

Page 47: ...ent Preliminary document Specifications in this document are tentative and subject to change Figure 47 Memory erase process 15 5 Writing the boot loader IPL to the Hyper Flash sector 1 Follow the same...

Page 48: ...CL0 I2C0 PMIC HDMI transmitter GP4_1 SDA0 I2C0 PMIC HDMI transmitter GP1_0 INT from PMIC Interrupt GP1_20 INT from HDMI Interrupt GP5_0 QSPI0_SPCLK QSPI0 GP5_5 QSPI0_SSL QSPI0 GP5_1 QSPI0_MOSI_IO1 QSP...

Page 49: ...M Express CPLD GP0_3 MD03 MD function CoM Express CPLD GP0_4 MD04 MD function CoM Express CPLD GP0_5 MD05 MD function CoM Express CPLD GP0_6 MD07 MD function CoM Express CPLD GP0_7 MD08 MD function Co...

Page 50: ...ss GP3_15 CoM Express GP3_16 CoM Express GP0_8 CoM Express GP0_9 CoM Express GP0_10 CoM Express GP0_11 CoM Express GP0_12 CoM Express GP0_13 CoM Express GP0_14 CoM Express GP0_15 CoM Express GP0_16 Co...

Page 51: ...customer can use the V3M Starter Kit as a mother board and implement its own products For this reason the V3M Starter Kit has been designed following the standard form factor CoM Express Note that onl...

Page 52: ...m This issue only affects the boards with S N 0001 through 0025 Newer versions of the board do not show this behavior The affected boards may be updated to overcome this issue 18 5 Multiplexors and Sw...

Page 53: ...54 January 24 2019 Under development Preliminary document Specifications in this document are tentative and subject to change 19 Attachments 19 1 Schematic 19 2 Mechanical drawing 19 3 CoM Express pin...

Page 54: ...rce selection Errata corrected on switch setting for QSPI Some drawings have been newly formatted Changes on text Product order number 2 20 Jan 21 2019 Figure 24 contains an error on version 2 00 Has...

Page 55: ...V3M Starter Kit Hardware Manual Publication Date Rev 2 30 January 24 2019 Published by Renesas Electronics Corporation...

Page 56: ...ADAS Group R12UT0003ED0230...

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