P9415-R-EVK Evaluation Kit
R16UH0015EU0100 Rev.1.0
May 27, 2021
Page 17
11.5 GP0/PWRGD Pin
The GP0 pin is a digital output referenced to LDO1P8. The AP can use the power good signal to turn on the
charging connection indicator or other system functions. Power good (PWRGD) pin is pulled low by default. In
BPP mode, the power good pin is pulled high when MLDO is enabled. In EPP mode, the power good pin is
pulled high at the end of the negotiation phase by default. It can be configured to be pulled high when MLDO
Vout is enabled.
11.6 GP1/Q Main Pin and GP3/Q Offset Pin
GP1 and GP3 are digital inputs used to configure Q factor value by resistor combination. If both GP1 and GP3
are low (< 0.2V), the P9415-R reports the default value programmed in the firmware. Q is 30 in the default
configuration and can be changed with a P9415-R Wireless Power Pro GUI; otherwise, the default Q factor value
is decided by the following tables.
Table 5. Q Factor Main – GP1
GP1
≥
Vmin
GP1 < Vmax
Q_Main
Pup(R)
Pdown(R)
0.2
0.55V
30
100K
27K
0.55V
0.90V
40
100K
68K
0.90V
1.25V
50
100K
150K
1.25V
1.60V
60
47K
180K
1.60V
1.98V
70
47K
NP
Table 6. Q Factor Offset – GP3
GP3
≥
Vmin
GP3 < Vmax
Q_Offset
Pup(R)
Pdown(R)
0V
0.2V
+0
NP
47K
0.2
0.55V
+1
100K
27K
0.55V
0.90V
+2
100K
68K
0.90V
1.25V
+4
100K
150K
1.25V
1.60V
+6
47K
180K
1.60V
1.98V
+8
47K
NP
For example, if both GP1 and GP3 are pulled up, the reported Q factor value is 78(70+8). The AP can also
change the reported Q factor by writing to register 0x55 before the negotiation phase.
