Renesas P9235A-RB, Layout Manual

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P9235A-RB Layout Guide
© 2019 Integrated Device Technology, Inc 5 March 19, 2019
Figure 3. Actual Placement for the P9235A-RB EVK. Select Critical Components are circled in Yellow
There are many things to take note of on this top layer with respect to creating an optimal layout (notes refer to the listing embedded in
Figure 3):

Closeness of C
IN
and Cboost caps to their respective pins (notes 1,6,15)

Tight (small) AC loops of FETs in relation to the LC tank (notes 9-12)

Tight loops of the FETs in relation to the H bridge Cin capacitors (notes 9,10)

Closeness of current and voltage demodulation to the IC (notes 5,13)

Closeness of H bridge FET gate driver resistors to the IC (note 14)

Tight loop of LC of 5V switching regulator for low loop inductance/noise (note 2)

Closeness of L to its respective switching node for minimum noise (note 2)

The H bridge FETs produce the most heat. Therefore, FET GND pads are connected to GND with the maximum number of 10mil vias for
the best thermal performance.