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Rev.1.00  2003.05.08 page 10 of 23

M65881AFP

OUTL1, OUTL2, OUTR1 and OUTR2 are pulse output modulated 

∆Σ

output to PWM signal. 

These pins are connected to external Power Driver ICs.The PWM output can be selected  
PWM Output Format 1, 2, 3 and 4 by serial control data(System1 mode, bit22,23 ).

PWM Output Form1 : General Modulation
PWM Output Form2 : Symmetrical Modulation
PWM Output Form3 : Modulation returned with time domain.

( The rise and fall edge of Lch and Rch in a term are reverse.)

PWM Output Form4:  Modulation returned with time domain.

( The rise and fall edge of Lch and Rch in a term are same timing.)

In each 4 forms, the rate and bit length of PWM Output can be changed.
Moreover, an output mute function and an output pins reverse function 
can be controlled by the pin setting or serial control.
Refer to pin setting of the following page about a phase of the PWM output 
for Power Stage and Headphone.
The PWM output control is shown in the following table.

PWM output control

Item

Operation

Setting Operation

Output Form

Operating Rate

and Data Bit Length

( Common setting for
Power Stage and
Headphone )

Output Muting

Reverse Output

Pins Function

Output Form Selection

1,2,3,4

Select to

16fso/6bit ,16fso/5bit ,32fso/5bit

from operating rate and data bit

length of 

∆Σ

.

PWM operation are synchronized

by this setting.

Duty 50% Mute

( Selectable common and
independent setting for Lch/ Rch.)

Absolute Zero Mute

Reverse on Lch and Rch of 
output pins (Common setting for 
Power Stage and Headphone)

Set up by the serial control system 1 mode
bit 22,23 (PWM MODE 0 and 1).
(Refer to system 1 mode(Page16) for details)

Set up by the serial control  system 2 mode bit16
and bit17.
( Refer to system 2 mode(Page 18) for details.)

< Common setting for Lch / Rch >
Set NSPMUTE pin "L" or set up by serial control "
System 2 mode bit14 (NSPMUTE) "H".

<  Independent Setting for Lch / Rch >
Set up by serial control Gain Control Mode bit9,10

(NSPMUTEL,NSPMUTER) "H" .

( Refer to Page 11,18 and 13 for details)

Set up by serial control system2 mode
bit15(PGMUTE) "H".

(See system2 mode(Page 18) )

Set up by serial control system2 mode bit9
(CHSEL).

Set up by serial control system2 mode bit12
(CHRSEL).

( Common setting for Power
Stage and Headphone)

Reverse for R1 and R2 of
output pins.

( Only enable for Power Stage.)

7. OUTL1, OUTL2, OUTR1, OUTR2

( Common setting for
Power Stage and
Headphone )

Summary of Contents for M65881AFP

Page 1: ...ith Exponential Approximate Curve Correspondence to Output for Headphone SYSTEM BLOCK DIAGRAM APPLICATION DVD Receiver AV Amplifier RECOMMENDED OPERATING CONDITIONS Logic Block 1 8V 10 PWM Buffer Bloc...

Page 2: ...Vdd SFLAG TEST2 TEST1 HPOUTR2 HPVssR HPOUTR1 HPVddR HPOUTL2 HPVssL HPOUTL1 HPVddL XVss XfsoIN XVdd VssLR OUTR2 OUTR1 VddR 1 8V system OUTL1 BFVss XfsiIN FsoCKO FsoI 3 3V system 3 3V system 3 3V system...

Page 3: ...UTR2 OUTL2 Sampling Rate Converter Gain Control DATA BCK LRCK S C D T S C S H I F T S C L A T C H 18 17 16 2 41 39 4 I N I T N S P M U T E X f s i I N Clock Generator Primary Clock Generator Secondary...

Page 4: ...g Temperature 3 6 Operating Frequency PWMVdd 3 0 3 3 Supply Voltage 3 3V system XVdd XOVdd PWM Output for Power Stage Headphone V Parameter Symbol Conditions Min Typ M Unit VIH3 BFVdd 3 0 to 3 6V 0 75...

Page 5: ...D GND Reference characteristic S N THD N 102dB typ 0 002 typ Conditions Input 1kHz 0dB Full scale sine wave FS Primary clock 44 1kHz Secondary clock 48kHz PWM Output format 1 AC dithering E DC ditheri...

Page 6: ...Input PCM Signal 3 3V 19 BFVdd Power Supply for Input Output 3 3V Buffer 20 BFVss GND for Input Output 3 3V Buffer 21 XfsiIN I Primary Master Clock Input 256fsi 512fsi 3 3V 22 FsoCKO O Secondary Fso...

Page 7: ...ing figures LRCK BCK MSB 16 cycle DATA 16bit MSB 16 cycle 1 fsi 1 2fsi 1 4fsi Left Right DATA 24bit MSB MSB 24 cycle 24 cycle MSB DATA 20bit MSB 20 cycle 20 cycle LSB LSB LSB LSB LSB LSB MSB first rig...

Page 8: ...e and master clock frequency Input signal and primary clock are related to synchronization The primary clock frequency are 512 or 256 times as much as the input signal fsi 32k 44 1k and 48k The primar...

Page 9: ...SYNC flag Serial Control System2 Mode bit6 rise edge too While re synchronizing SFLAG pin outputs H and data is muted inside In case of using Multiplex for multi channel application and Single for 2ch...

Page 10: ...Common setting for Power Stage and Headphone Output Muting Reverse Output Pins Function Output Form Selection 1 2 3 4 Select to 16fso 6bit 16fso 5bit 32fso 5bit from operating rate and data bit lengt...

Page 11: ...function system2 mode bit6 11 TEST1 TEST2 TEST1 and TEST2 pins are test input for factory shipping test of M65881AFP TEST1 and TEST2 pins must be tied to L level on usual operation 12 Power supply and...

Page 12: ...dd BFVdd Master clock XfsoIN XfsiIN INIT SCDT SCSHIFT SCLATCH Over 5msec 1 Over 0sec 2 Over 2 fso 3 Power ON Power OFF 1 After a power supply and Master clock become to stable INIT pin must be L over...

Page 13: ...ects by input signal level and limit gain control The limit Value is set by Gain control Mode bit5 6 NSLMT1 2 and System2 Mode bit17 NSOBIT Limit value setting of output for gain control and bit5 6 NS...

Page 14: ...value setting continuously In case of Gain value setting continuously for example of setting L Rch independently please take the interval time pulse interval time of SCLATCH signal more than 1 fso For...

Page 15: ...so 10 416 sec step transition term are following From Maximum value 10100b 11111111b to Minimum value 00000b 00000000b 2816T 29 333msec From 0dB value 10000b 10000000b to Minimum value 00000b 0000000b...

Page 16: ...4 15 16 17 18 19 20 ASYNC1MODE Asynchronous Detection Flag for Primary Side Zero Mute PWM duty50 L 21 22 PWMMODE0 Selection for PWM Output type L 23 PWMMODE1 L 24 PWMHP Phase of HPOUTL1 R1 based on PW...

Page 17: ...as MCKSEL L in advance is required 2 Serial control system1 mode bit22 23 PWMMODE0 1 H L When a setup of both 1 and 2 is completed it changes to Form2 When 2 is set up before 1 The term until a setup...

Page 18: ...Secondary master clock 512fso Non dithering L L bit Flag name Functional Explanation H L INIT 1 MODE1 Mode settiing1 H fixed 2 MODE2 Mode setting2 L fixed 3 IMCKSEL Input master clock Selection 512fs...

Page 19: ...MUTE Fixed PWM duty 50 Mute L Mute release H Mute This function exists also in a pin by the same name This Mute function can be set either NSPMUTE flag or NSPMUTE pin Refer to Page13 about a relation...

Page 20: ...CLATCH twh twhl twl duty XfsoIN XfiIN twh twhl Item Symbol Condition Min Typ Max Unit XfsoIN Duty Ratio duty XfsoIN 40 50 60 512fsi 30 50 70 256fsi 40 50 60 SCSHIFT Pulse time tw SCSHIFT 160 nsec SCDT...

Page 21: ...elect L 1024Fso H 512Fso Flag Output Secondary Clock output Oscillator Power Driver Power Driver Initialize Control Mute Control Input Mode Select2 M65881AFP LRCK BCK DATA XfsiIN Primary Clock OUTL1 O...

Page 22: ...E Plastic 42pin 450mil SSOP Symbol Min Nom Max A A 2 b c D E L L 1 y Dimension in Millimeters H E A 1 I 2 25 0 05 0 13 0 3 17 2 8 63 11 3 0 27 1 0 2 3 0 15 0 5 17 4 8 8 0 93 11 5 0 765 1 43 11 4 2 4 0...

Page 23: ...n The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from...

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