R01UH0136EJ0210 Rev.2.10
Page 539 of 800
Jul 31, 2012
M16C/64A Group
25. Multi-master I
2
C-bus Interface
25.2.4
I2C0 Control Register 0 (S1D0)
BC2 to BC0 (Bit counter) (b2-b0)
Bits BC2 to BC0 become 000b (8 bits) when a start condition is detected.
When the ACKCLK bit in the S20 register is 0 (no ACK clock), and data for the number of bits selected
by bits BC2 to BC0 is transmitted or received, bits BC2 to BC0 become 000b again.
When the ACKCLK bit in the S20 register is 1 (ACK clock), and data for the number of bits selected and
an ACK is transmitted or received, bits BC2 to BC0 become 000b again.
ES0 (I
2
C-bus interface enable bit) (b3)
The ES0 bit enables the I
2
C interface.
When the ES0 bit is set to 0, the I
2
C interface becomes as follows:
•
Pins SDAMM and SCLMM: I/O ports or other peripheral pins
•
The S00 register is write disabled.
•
The I
2
C-bus system clock (hereinafter called fVIIC) stops.
•
S10 register
ADR0 bit: 0 (general call not detected)
AAS bit: 0 (slave address not matched)
AL bit: 0 (arbitration lost not detected)
PIN bit: 1 (no I
2
C-bus interrupt request)
BB bit: 0 (bus free)
TRX bit: 0 (receive mode)
MST bit: 0 (slave mode)
b7 b6 b5 b4
b1
b2
b3
I2C0 Control Register 0
Symbol
S1D0
Address
02B3h
Bit Symbol
Bit Name
RW
Reset Value
00h
b0
Function
ES0
ALS
RW
—
(b5)
RW
IHR
TISS
I
2
C-bus interface reset bit
0: I
2
C-bus input
1: SMBus input
I
2
C-bus interface pin input
level select bit
RW
I
2
C-bus interface enable bit
0: Disabled
1: Enabled
Data format select bit
0: Addressing format
1: Free data format
BC0
Bit counter (number of
transmitted/received bits)
BC1
BC2
b2 b1 b0
0 0 0: 8
0 0 1: 7
0 1 0: 6
0 1 1: 5
1 0 0: 4
1 0 1: 3
1 1 0: 2
1 1 1: 1
RW
RW
RW
RW
RW
0
Reserved bit
0: Reset is released (automatically)
1: Reset
Set to 0.
Summary of Contents for M16C/60 Series
Page 853: ...M16C 64A Group R01UH0136EJ0210...
