ISL81802EVAL3Z
2. PCB Layout Guidelines
R16UH0004EU0100 Rev.1.00
Page 5 of 19
Sep.15.20
2.
PCB Layout Guidelines
Careful attention to Printed Circuit Board (PCB) layout requirements is necessary for successful implementation
of an ISL81802 based DC/DC converter. The ISL81802 switches at a high frequency; therefore, the switching
times are short. At these switching frequencies, even the shortest trace has significant impedance and the peak
gate drive current rises significantly in an extremely short time. The transition speed of the current from one
device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and ringing.
Careful component selection and proper PCB layout minimizes the magnitude of these voltage spikes.
The following are critical components
when using the ISL81802 DC/DC converter:
• Controller
• Switching power components
• Small-signal components
The switching power components are the most critical to the layout because they switch a large amount of energy
that tend to generate a large amount of noise. The critical small-signal components are those connected to
sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.
Complete the following steps to optimize the PCB layout.
1. Place the input capacitors, FETs, inductor, and output capacitor first. Isolate these power components on
dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output
high frequency decoupling ceramic capacitors close to the MOSFETs.
2. If signal components and the IC are placed separately from the power train, Renesas recommends using full
ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise,
use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND
together close to the IC.
Note: DO NOT
connect them together anywhere else.
3. Keep the loop formed by the input capacitor, the top FET, and the bottom FET as small as possible.
4. Ensure the current paths from the input capacitor to the FETs, the power inductor, and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the lower FETs. The low-side FETs gate drive connections should be
short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.
6. Place the VDD bypass capacitor close to the VDD pin of the IC and connect its ground end to the PGND pin.
Connect the PGND pin to the ground plane by a via.
Note: DO NOT
connect the PGND pin directly to the SGND EPAD.
7. Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.
8. Place the output capacitors as close to the load as possible. To avoid inductance and resistances, use short,
wide copper regions to connect output capacitors to load.
9. Use copper filled polygons or wide, short traces to connect the junction of the upper FET, lower FET, and output
inductor. Keep the PHASE nodes connection to the IC short.
Note: DO NOT
unnecessarily oversize the copper
islands for the PHASE nodes. Because the phase nodes are subjected to extreme dv/dt voltages, the stray
capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.
10. Route all high-speed switching nodes away from the control circuitry.
11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. Connect all small
signal grounding paths including feedback resistors, current monitoring resistors and capacitors, soft-starting
capacitors, loop compensation capacitors and resistors, and EN pull-down resistors to this SGND plane.
12. Use a pair of traces with minimum loop for the input or output current sensing connection.
13. Ensure the feedback connection to the output capacitor is short and direct.
