E2, IE850A
6. Internal Circuit of the E2 Emulator
R20UT4140EJ0300 Rev.3.00
Page 37 of 41
Oct.09.20
6.Internal Circuit of the E2 Emulator
The internal interface circuit related to the communications interface between the E2 emulator and user
system is shown in Figure 6-1. Please refer to the figure when determining parameters in board design.
Figure 6-1 Interface Circuits in the E2 Emulator (4-Pin LPD, 2-Wire UART, CSI)
Emulator
control
circuit
74LVC1T45
74LVC1T45
74LVC1T45
74LVC1T45
74LVC8T245
74LVC1T45
74LVC1T45
74LVC8T245
74LVC1T45
NFL21SP
Noise filter
47Ω
1MΩ x6
3.3V
47Ω
47Ω
47Ω
47Ω
NFL21SP
Noise filter
47Ω
3.3V
100
k
Ω
Self-recovering
fuse
8 TVDD
1 LPDCLK
5 LPDO
3 TRST
9
-
11 LPDCLKO
4 FPMD0
7 LPDI/FPDR
10 EVTO
14 GND
13 RESET
2,12 GND
6
-
74LVC8T245
47Ω
1MΩ
14-pin connector
47Ω
NFL21SP
Noise filter
100kΩ
0.1μF
74LVC1T45
20-pin connector
1
4
16
6
2
12
18
8
20
9
10
14
3,5,15,
17,19
3
1
SW is on 1 side
3MΩ x2
Power-supply circuit
(only in the mode to
supply power)