491
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
B. Clocking
This appendix describes device behavior outside the
RapidIO Interconnect Specification (Revision 1.3)
recommended operating line rates and clock frequencies.
The following topics are discussed:
•
“Line Rate Support” on page 491
•
“P_CLK Programming” on page 495
B.1
Line Rate Support
The Tsi576 supports all of the
RapidIO Interconnect Specification (Revision 1.3)
specified line rates of
1.25, 2.50, and 3.125 Gbaud. The device also supports line rates that are outside of the RapidIO
specification. The ability to support multiple line rates gives the Tsi576 flexibility in both application
support and power consumption.
shows the supported line rates for the Tsi576. The Serial Port Select pin, SP_IO_SPEED[1,0]
must be set to the values shown in
to achieve the documented line rates.
Table 53: Tsi576 Supported Line Rates
a
S_CLK_p/n (MHz)
Baud Rate (Gbaud)
SP_IO_SPEED[1,0] Bit
Settings
Register Settings
153.60
1.2288
CPRI Line Rate
0,0
-
153.60
1.536
OBSAI Line Rate
0,1
-
153.60
2.4576
CPRI Line Rate
0,1
-
153.60
3.0720
CPRI Line Rate
1,0
-
156.25
1.2500
Standard RapidIO Line Rate
0,0
-
156.25
2.5000
Standard RapidIO Line Rate
0,1
-
156.25
3.1250
Standard RapidIO Line Rate
1,0
-
