6. Event Notification > Interrupt Notifications
140
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
6.7.1
INT_b Signal
At the top level of the interrupt hierarchy is the external interrupt signal INT_b. This active low signal
is asserted when any fully enabled interrupt occurs. The INT_b signal remains asserted until all
interrupts are cleared within the device.
The INT_b signal is driven by the
“Global Interrupt Status Register” on page 390
. The INT_b signal is
asserted when any bit within the Global Interrupt Status register is set and its corresponding enable bit
in the
“Global Interrupt Enable Register” on page 392
is also set. If an interrupt in the Global Interrupt
Enable register is not enabled, the bit in Global Interrupt Status register is still set when an interrupt
occurs, but INT_b is not asserted.
Interrupts can be cleared by either writing the interrupt status register bit or by disabling that interrupt.
When a previously asserted interrupt is disabled, the interrupt bit remains set in the interrupt status
register, but the interrupt is no longer propagated up the interrupt hierarchy.
6.7.2
Global Interrupt Status Register and Interrupt Handling
“Global Interrupt Status Register” on page 390
must be read to determine why the interrupt was
raised. Interrupt causes in the Global Interrupt Status register allow the interrupt service routine to
decide which port raised an interrupt. The I
2
C controller has a separate indicator bit, as it is not
associated with any port.
Two functions that are port specific have separate indicator bits to allow for faster handling. These
functions are Multicast Event Control Symbol reception, and reception of a valid reset control symbol
sequence. Both Multicast Event Control Symbol and Reset Control Symbol interrupts can be cleared
with one register write to the status bit in the broadcast address of the
.
After the software has read the Global Interrupt Status register and determined which port has an
interrupt pending, the port’s interrupt status registers must be accessed to determine the exact cause.
Each port contains an interrupt status register (see
“RapidIO Port x Interrupt Status Register” on
) and an associated interrupt enable register (see
“RapidIO Port x Control Independent
). When an interrupt occurs within a port, the associated bit for that interrupt is
set within the interrupt status register regardless of the setting of the interrupt enable register. The port
only notifies the
“Global Interrupt Status Register” on page 390
if that interrupt is enabled.
The RapidIO defined status registers are discussed in
“Other Interrupts Types and Interrupt
.
6.7.2.1
Other Interrupts Types and Interrupt Handling
TEA events have a separate register which allows an interrupt handler to quickly determine on which
port the TEA occurred. Similarly, multicast latency errors have a separate register to indicate which
port is unable to receive multicast packets.
Ti
p
Because there is only one logical layer error per device, the LOG_ERR bit is also in
the
“Global Interrupt Status Register” on page 390
.
