Renesas IDT Tsi574, User Manual

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4. Internal Switching Fabric > Functional Behavior 84
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
4.2 Functional Behavior
The ISF is responsible for transporting packets from an ingress port to an egress port and to and from
the multicast engine. When RapidIO packets arrive at the ingress ports, the Tsi574 performs several
tests to ensure the packet is valid. If a packet passes these tests, the ingress port consults its
destination ID lookup table (LUT) to determine the egress port for the packet. The ISF transfers entire
packets without interruption in store-and-forward mode (for more information, see
“Transfer Modes”
on page 85 ).
The ISF is a crossbar switch, which means that an ingress port can only send one packet at a time to the
ISF, and an egress port can only receive one packet at a time from the ISF. However, the ISF can
simultaneously transport packets from multiple independent ingress ports and egress port pairs
simultaneously. This architecture has no shared memory area that holds packets.
Since many ingress ports can attempt to send a packet to the same egress port, queuing is required at
the ingress ports. Special arbitration algorithms at both the ingress and egress sides of the fabric ensure
that head-of-line blocking is avoided in these queues.
Queuing is also required at the egress ports. Packets can accumulate when an egress port has to
re-transmit a packet (for example, due to a CRC error), or when a high-bandwidth ingress port sends
traffic to a lower-bandwidth egress port.
Queuing is also required to support multicast functionality. The ISF supports dedicated connections
between each ingress port and the multicast work queue and a dedicated connection between the work
queue and the broadcast buffers. This allows packets to be replicated in parallel. For more information
on multicast, refer to
“Multicast” on page 101 .
Figure 16 illustrates a conceptual block diagram, showing the relationship of the components within
the ISF.
Figure 16: ISF Block Diagram
Ti
p
Refer to the “Serial RapidIO Interface” on page 35 for more information how RapidIO
packets are tested as valid.
Source Port Modules Destination Arbiters
Switching Fabric
(Fully connected mesh)
RR and SP
Schedulers
Packet Data
Received
From Ingress
Interfaces Packet
Data Sent
To Egress
Interfaces
“VOQ”
“VOQ”
“VOQ”