Renesas HD151TS207SS Page 24 Specification Sheet Download

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HD151TS207SS

Rev.1.00, Apr.25.2003, page 24 of 38

Clock Stop Timing Diagram

Iref (Controled by Byte2[6])

Iref (Controled by Byte2[5:3])

Tristate

(Controled by Byte2[6])

Tristate

PCI_STOP#

PCI_F

PCI

SRC (Stoppable)

PCI_STOP# Assertion/De-assersion

PCI_STOP# Assertion/De-assertion Waveforms

Low

PWRDWN#

CPU (Stoppable)

CPU# (Stoppable)

CPU (Stoppable)

PWRDWN# Assertion/De-assersion

PWRDWN# Assertion/De-assertion Waveforms

Iref

< 1.8 ms

PWRDWN#

PWRDWN# Functionality

CPU#

CPU

SRC

SRC#

3V66

66MHz

Normal Normal Normal

Float

Low

PCIF/PCI

33MHz

Low

USB/DOT

48MHz

Low

REF

14.318MHz

Low

SRC (Stoppable)

SRC# (Stoppable)

Float

(Controled by Byte2[5:3])

Float

Normal

Iref:2

or Float

Iref:2

or Float

Summary of Contents for HD151TS207SS

Page 1: ...lectable 100 MHz 200 MHz 6 copies PCI clocks and 3 copies PCIF clocks 3 3V 33 3 MHz 1 copy PCI clock 3 3 V selectable 33 3 MHz 25 MHz 1 copy USB clock 3 3 V selectable 48 MHz 24 MHz 1 copy DOT clock 3...

Page 2: ...1 00 Apr 25 2003 page 2 of 38 Key Specifications Supply Voltages VDD 3 3 V 5 CPU clock cycle to cycle jitter 125ps SSC Disabled CPU clock group Skew 100ps 3V66 clock group Skew 250psmax PCI clock gro...

Page 3: ...V66_0 RESET 3V66_1 VDD_3V66 PCIF_2 11 12 13 14 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VSS_48 VDD_48 VTT_PWRGD SRC SRC CPU_1 CPU_0 CPU_0 V...

Page 4: ...XTAL output Don t connect when an external clock is applied at XTAL_IN FS2 PCIF_ 0 1 7 8 INPUT OUTPUT Frequency select latch input pin Free running PCI clock 3 3 V output PCIF_2 9 OUTPUT Free running...

Page 5: ...Hz output 1 24 MHz 0 48 MHz 24_48 MHz clock 3 3 V output FS3 DOT_48 32 INPUT OUTPUT Frequency select latch input pin DOT_48 clock 3 3 V output VTT_PWRGD 35 INPUT PULL UP Qualifying input that latches...

Page 6: ...pin 3 3 V VDD_48 3 3 V VDD_A VSS_48 VSS_A 6 3 3V VDD 6 VSS VSS_IREF IREF PCI 6 0 SRC SRC SEL48_24 FS_4 3 2A B SEL33_25 MODE TEST_CLK SEL66_48 SEL100_200 VTT_PWRGD PWRDWN SAFE_F PCI_STOP SCLK SDATA In...

Page 7: ...S_A Low at power up 1 FS_A High at power up R X See Table 1 Table1 Clock Frequency Function Table Byte6 Bit5 FS_A FS_B CPU MHz SRC MHz 3V66 MHz PCIF PCI MHz REF0 REF1 MHz USB DOT MHz Note 0 0 0 100 10...

Page 8: ...1 3 Reserved RW 1 2 CPU2 Output enable 0 Disabled tristate 1 Enabled RW 1 1 CPU1 Output enable 0 Disabled tristate 1 Enabled RW 1 0 CPU0 Output enable 0 Disabled tristate 1 Enabled RW 1 Byte2 Control...

Page 9: ...X Running Running SRC 1 0 0 X Running Driven Iref x6 See Note1 SRC 1 0 1 X Running Tristate SRC 0 X X 0 Driven Iref x2 Driven Iref x2 See Note1 SRC 0 X X 1 Tristate Tristate Note 1 Iref VDD 3Rr 3 3 3x...

Page 10: ...0 Disabled 1 Enabled RW 1 Byte5 Control Register Bit Description Contents Type Default Note 7 DOT_48MHz Output Enable 0 Disabled 1 Enabled RW 1 6 Reserved RW 1 5 VCH Select 66MHz 48MHz 0 3V66 mode 1...

Page 11: ...2 Vendor ID Bit2 Vendor Specific R 1 1 Vendor ID Bit1 Vendor Specific R 1 0 Vendor ID Bit0 Vendor Specific R 1 Byte8 Read Back Byte Count Register Bit Description Contents Type Default Note 7 Read bac...

Page 12: ...SC1 ON RW 0 5 Clock Frequency Control Bit4 Latched input PCIF_1 at Power ON RW X 4 Clock Frequency Control Bit3 Latched input DOT48 at Power ON RW X 3 Clock Frequency Control Bit2 Latched input PCIF_0...

Page 13: ...3 34 11 0 1 0 1 1 149 36 100 02 66 68 33 34 12 0 1 1 0 0 152 91 100 02 66 68 33 34 13 0 1 1 0 1 156 47 100 02 66 68 33 34 14 0 1 1 1 0 160 03 100 02 66 68 33 34 15 0 1 1 1 1 163 58 100 02 66 68 33 34...

Page 14: ...d if B23 1 0 frequency selection is changed to these setting and PWRDWN SAFE_F pin to High frequency selection is changed back to the last mode R X Byte11 Control Register Bit Description Contents Typ...

Page 15: ...0 and B14 6 0 are able to be changed at B12 2 1 R W 0 1 PLL1 N1 Divider Control Bit9 N1 9 R W 0 0 PLL1 N1 Divider Control Bit8 N1 8 R W 0 See Note 1 Note 1 B12 1 0 B13 7 0 and B14 6 0 must be written...

Page 16: ...tput Frequency Select Bit 0 33 3 MHz 1 25 MHz R W 0 6 USB_48 Output Frequency Select Bit 0 48MHz 1 24 MHz R W 0 5 SAFE_F Input mode select Bit 0 PWRDWN input mode 1 SAFE_F input mode Default is PWRDWN...

Page 17: ...00 1 4 0101 1 5 0110 1 6 0111 1 7 1000 1 8 1001 1 9 1010 1 10 1011 1 11 R W X Byte17 Control Register Bit Description Contents Type Default Note 7 Reserved R W 0 6 Reserved R W 0 5 Reserved R W 0 4 PL...

Page 18: ...it1 R W 0 0 VCO2 Frequency Control Bit0 These bits are 1MHz digit of VCO2 frequency 0000 0 0001 1 1001 9 R W 0 See Note 1 Note 1 B17 3 0 and B18 7 0 must be written together at writing B18 in every ca...

Page 19: ...ncy Read Bit7 R 0 6 VCO2 Frequency Read Bit6 R 0 5 VCO2 Frequency Read Bit5 R 0 4 VCO2 Frequency Read Bit4 Calculation result of VCO2 frequency 1 MHz digit 0000 0 0001 1 1001 9 R 0 3 VCO2 Frequency Re...

Page 20: ...Byte23 Control Register Bit Description Contents Type Default Note 7 Watchdog Enable Control Bit 0 Disable Pin22 3V66_0 output 1 Enable Pin22 RESET output R W 0 6 RESET Reverse Control Bit 0 Normal 1...

Page 21: ...0 Byte25 Control Register Bit Description Contents Type Default Note 7 CPU Clock Skew1 Control Bit3 R W 1 6 CPU Clock Skew1 Control Bit2 R W 0 5 CPU Clock Skew1 Control Bit1 R W 0 4 CPU Clock Skew1 Co...

Page 22: ...0 Skew1 is Normal Skew Delay Ahead 1000 0 0ns 0111 0 4ns 1001 0 4ns 0110 0 8ns 1010 0 8ns 0101 1 2ns 1011 1 2ns 0100 1 6ns 1100 1 6ns 0011 2 0ns 1101 2 0ns 0010 2 4ns 1110 2 4ns 0001 2 8ns 1111 2 8ns...

Page 23: ...1 Late R W 0 1 PCI_1 Skew Select Bit 0 Normal 1 Late R W 0 0 PCI_0 Skew Select Bit 0 Normal 1 Late R W 0 See Note 1 Note 1 Normal Skew1 B26 3 0 Late Skew1 B26 3 0 Skew2 B26 7 4 Byte29 Control Register...

Page 24: ...CI_STOP Assertion De assertion Waveforms Low PWRDWN CPU Stoppable CPU Stoppable CPU Stoppable PWRDWN Assertion De assersion PWRDWN Assertion De assertion Waveforms 6 Iref 6 Iref 1 8 ms PWRDWN PWRDWN F...

Page 25: ...tor will acknowledge Renesas clock gen sends Low 1 6 Controller host sends a byte count N 1 7 Renesas clock generator will acknowledge Renesas clock gen sends Low 1 8 Controller host sends data from b...

Page 26: ...Controller host sends a stop bit Start bit 1 bit 1 bit 1 bit 1 bit 1 bit 7 bits 8 bits 7 bits 1 bit Restart bit Slave address Slave address R W D2 h R W D3 h Ack 1 bit Ack 1 bit Ack 1 bit Ack 1 bit Ac...

Page 27: ...to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposur...

Page 28: ...DATA SCLK Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics Serial Input port Ta 0 C to 70 C VDD 3 3 V...

Page 29: ...13 89 mA Voh Z 0 695 V 50 Ioh x2 4 63 mA Voh Z 0 232 V 50 AC Electrical Characteristics CPU CPU Clock CPU at 0 7V Timing Ta 0 C to 70 C VDD 3 3 V CL 2 pF Rs 33 2 Rp 49 9 Item Symbol Min Typ Max Unit T...

Page 30: ...Ioh shown in below Ioh VDD 3Rr 3 3 3x475 2 32 mA Ioh x6 13 89 mA Voh Z 0 695V 50 Ioh x2 4 63 mA Voh Z 0 232V 50 AC Electrical Characteristics SRC SRC Clock SRC at 0 7V Timing Ta 0 C to 70 C VDD 3 3 V...

Page 31: ...hown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics 3V66 Buffer Ta 0 C to 70 C VDD 3 3 V CL 30 pF Item Symbol Min Typ Max Unit T...

Page 32: ...5 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics PCI PCIF Clock Ta 0 C to 70 C VDD 3 3 V CL 30 pF...

Page 33: ...utput Current IOL 29 mA VOL 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics USB VCH 48MHz Cloc...

Page 34: ...Output Current IOL 29 mA VOL 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics DOT Clock Ta 0 C...

Page 35: ...tput Current IOL 30 mA VOL 1 95 V Note 1 For conditions shown as Min or Max use the appropriate value specified under recommended operating conditions AC Electrical Characteristics REF Clock Ta 0 C to...

Page 36: ...CCS tcycle n 1 Fig 1 Cycle to Cycle Jitter 3 3V Single Ended Clock Output Clock Outx Clock Outy 1 5 V tskS 1 5 V Fig 2 Output Clock Skew 3 3V Single Ended Clock Output RP 49 9 RP 49 9 ZLT ZLC 50 RS 33...

Page 37: ...HD151TS207SS Rev 1 00 Apr 25 2003 page 37 of 38 Package Dimensions Unit mm 0 10 0 004 7 50 1 28 29 56 18 40 0 25 0 635 0 3 2 6 10 35 0 76 0 5 0 8 0 2...

Page 38: ...y Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corpora...

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