Renesas ForgeFPGA, User Manual

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ForgeFPGA Configuration Guide
Rev.1.0
May 31, 2022 Page 2
3. Introduction
An internal Configuration Wrapper is used to configure the ForgeFPGA core. The configuration can be done
from three different configuration bitstream sources:
–
External SPI/QSPI Flash
–
Internal OTP
–
MCU as a host
The ForgeFPGA Designer Software is used to generate bitstreams. The schematic in Figure 1 shows a block
diagram of the SLG47910 configuration block and the external MCU Host and QSPI Flash interface. The four
Configuration pins are GPIO3 (SPI_CLK), GPIO4(SPI_SS, Chip Select), GPIO5(SPI_SI, serial input) and
GPIO6(SPI_SO, serial output). GPIO9 is used as a Config Done signal.
Table 1 shows which modes activate the
SPI Master and SPI Slave blocks during configuration.
MCU
Host
QSPI
Flash
OTP
SPI
Master
SPI
Slave
Config Loader
FPGA Core
OTP
Programmer
Configuration Wrapper
conf
Q
D
SPI
otp_data_rd
otp_ctrl
op_data_wr
ctrl
ctrl
ctrl
tx_data
tx_data
ctrl
tx_data
4
Figure 1: SLG47910 Programming Interface
Table 1: Configuration Modes
Configuration Mode SPI Block Activated Clock Source
QSPI/SPI Master FPGA
MCU Slave MCU
READ OTP Slave External to FPGA
Write OTP Slave External to FPGA
4. General SPI Interface
A 4-wire SPI device has four signals (see Figure 2 ):
1. SCLK: Serial Clock (output from Master). When the master communicates with the slave, the data on MOSI
or MISO pin will be synchronized with the Serial Clock. In the SPI protocol, the master produces the clock. The
slave will only receive the clock, so the slave has no control over the serial clock, which is produced by the
master.
2. MOSI: Master-Out Slave-In (data output from master). MOSI is a data pin. This pin is used to transmit data
from the Master to the Slave device. Whenever the master sends data, that data will be collected over the MOSI
pin by the slave.