Renesas 8V19N49 Series Manual Download

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R31UH0005EU0100 Rev.1.0

Page 2

Jun 3, 2021

8V19N49x Hardware Design Guide

1. Overview

As indicated, this document provides board-level hardware design guidelines for the 8V19N49x product family.
The document also recommends power rail handling, loop filter calculation, and input/output termination. A
general schematic example is shown in

Figure 1

. A more detailed version is available upon request.

Figure 1. 8V19N490 Schematic Example

2. Power Rails

2.1

Bypass Capacitors

Bypass capacitors are required to filter out the system noise from switching power supplies and switching signal
interference from other parts of the system.

Figure 1

shows examples of bypass capacitors on the schematic. A

PCB layout example is also available upon request. The type of bypass capacitor will depend on the noise level
and noise frequencies in the system environment. The synthesizer output driver switching can also cause power
rail noise. These noises can also interfere with other parts of the circuit or cause spur on other output channels.

The bypass capacitor values are usually in the range of 0.01uF to 0.1uF; however, other values can be used.
Typical capacitor sizes are 0603, 0402, or 0201 with low ESR. The dielectric types typically are X5R or X7R. The
smaller size allows the capacitor to be placed close to the power pin and reduces the trace length. Some capacitor
vendors such as AVX provide online tools and models to provide the frequency response of the capacitors.

Figure 2

Figure 5

show the frequency response of various value capacitors provided by the capacitor supplier

AVX. The frequency response plot shows that the smaller value capacitor can filter out high frequency noise and a
larger value capacitor can filter out lower frequency noise. Typical power supply switching frequency can be

Place on the Top Layer

Layout Note: Place the bypass
capacitors (0201) next to the power
pins

VCO-VC

Place close to
the DUT

Close to
the pin

VCXO-VC

Place close to DUT Pins

Place close
toVCXO Pins 1

Close to the
pins if
possible

VCXO=122.88 MHz
LVPECL

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1R%XLOWLQ

7HUPLQDWLRQ

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&/.[Q&/.[,QSXWLQWHUIDFH([DPSOH

'LIIHUHQWLDO6LJQDO

6DPHFLUFXLWFDQEHGXSOLFDWHGIRU

&/.Q&/.LQSXW

Loop Filter values shown here are
example only. Other values can also
be used. It depends on the system
loop band width requirementn.

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HTXLSPHQWPRQLWRULQJHJSKDVHQRLVHPHDVXUHPHQW

Keep this trace from noisy source

Keep this trace from
noisy source

VDD_LCF(Clean)

LVPECL Termination Example

There are many way to
terminate LVPECL driver

VDD1

VDD_SYNC

VDD_QCLKB

VDD_QREFB

VDD_QCLKD

VDD_QREFD

VDD_QCLKE

VDD_SPI

VDD_CP2

VDD_LCV

VDD_QREFC

VDD_QCLKC

VDD_LCF

VDD_QCLKA

VDD_QREFA

VDD3

VCC_VCXO

VDD

VREG_3.3V

VDD_SPI

LFV

SDAT

nINT

nCS
SCLK

LOCK

LFV

Q_VCXO

nQ_VCXO

Q_VCXO

nQ_VCXO

R16

2.8K, 1%

Zo = 50

R51
50

VCXO_5mmx7mm_6pin_long_pad

VCONT

GND

VCC

R18
100

100p

C5
0.1u

C28
0.1u

C19

100p

C13
0.1u

TP1

100p

C17

High Impedance

R22
33k

R12

10K

C14

C4
0.1u

C29
0.1u

R15
10K

High Impedance Input

Zo = 50

C15

C32

0.1u

C31

33p

IDT8V19N490

nQCLKB0

QCLKB0

VDD_QCLKB

nQREF_B0

QREF_B0

nQCLK_B1

QCLKB1

VDD_QREFB

nQREF_B1

QREF_B1

VDD_CP

nOSC

VDD_OSC

QCLK_A1

nQCLK_A1

B10

LFV

OSC

GND_A8

QCLK_A0

nQCLKA0

A10

GND_C1

GND_C2

GND_C3

VDD_QREFD

SELSV

GND_C6

nINT

QCLK_A2

nQCLK_A2

C10

nQCLK_D

QCLK_D

VDD_CLLKD

nQREF_D

QREF_D

GND_D6

GND_D8

VDD_QREFA

VDD_CLKA

D10

GND_E1

GND_E2

VCC_SPI

nCS

SCLK

GND_E6

GND_E7

SDAT

QREF_A2

nQREF_A2

E10

nQREF_C0

QREF_C0

EXT_SYS

CLK3

CLK2

CLK1

CLK0

RES_CAL

QREF_A1

nQREF_A1

F10

nQREF_C1

QREF_C1

VDD_INP

nQCLK3

nQCLK2

nQCLK1

nCLK0

LOCK

QREF_A0

nQREF_A0

G10

VDD_CLKC

VDD_QREF_C

GND_H3

GND_H4

GND_H5

GND_H6

VDD_SYNC

GND_H8

GND_H9

GND_H10

H10

nQCLK_C0

QCLLK_C0

GND_J3

VDD_LCV

CR0

GND_J6

GND_J7

GND_J8

QCLK_E1

nQCLK_E1

J10

nQCLK_C1

QCLK_C1

GND_K3

VDD_LCF

LFFR

LFF

VDD_CPF

VDD_QCLKE

QCLK_E0

nQCLK_E0

K10

10K

C11

R10
5.1K

C7
100p

C16
0.1u

R14

10K

R24
np (49.9)

C38

0.1uF

C8
0.1u

C22
0.1u

JP1

LVDS Driver

R11

5.1K

R53
50

C12
0.1u

C24
0.1u

C37
1u

C35
4.7n

C30

0.1u

C23

0.1u

C39

100pF

C27

100p

R5
100

C10
0.1u

C2
0.1u

R13

2 x Zo

C18

0.1u

R19
np (49.9)

C6
0.1u

Zo = 50

C20

0.1u

R20

51k

100

C26
4.7u

C21
0.1u

Zo = 50

C34
27n

C1
0.1u

R52
50

QREFD0_N

QCLKE0_N

QCLKE1_P

QCLKB0_N

QCLKB1_P

LFF

CLK1

QREFA1_N

QCLKA2_P

QREFA2_N
QREFA2_P

QREFA0_P

QREFA0_N

QCLKE1_N

QCLKE0_P

QREFA1_P

QCLKC0_N

QCLKA0_P

QCLKA0_N

QCLKC0_P

QCLKA1_N
QCLKA1_P

QCLKA2_N

nCLK2

CLK2

CLK3

nCLK3

QCLKB1_N

QCLKB0_P

QCLKD0_N
QCLKD0_P

QREFB1_N

QREFB1_P

QREFB0_N

QREFB0_P

QREFD0_P

QREFC0_N
QREFC0_P

nCLK1

CLK0

QREFC1_N
QREFC1_P

LFFR

MCLK_P

MCLK_N

RES_CAL

EXT_SYS

VC
OE

QCLKx

nQCLKx

QCLKx

nQCLKx

QCLKA0

nQCLKA0

nCLK0

Summary of Contents for 8V19N49 Series

Page 1: ...5 3 2 3rd Order Loop Filter 6 3 3 Loop Filter Calculation Examples 7 3 3 1 Loop Filter for VCXO PLL 7 3 3 2 Loop Filter for VCO PLL 10 4 Input Output Interface 11 4 1 Input Termination for Reference Clock Input 11 4 2 Output Terminations for QCLK and QREF Drivers 13 4 2 1 LVPECL Type Driver Terminations 13 4 2 2 LVDS Type Driver Terminations 15 4 2 3 DC Coupling Interface for QREF Driver 15 5 Sche...

Page 2: ...U RKP ODE HTXLSPHQW PRQLWRULQJ H J SKDVH QRLVH PHDVXUHPHQW Keep this trace from noisy source Keep this trace from noisy source VDD_LCF Clean LVPECL Termination Example There are many way to terminate LVPECL driver There are many way to terminate LVPECL driver VDD1 VDD_SYNC VDD_QCLKB VDD_QREFB VDD_QCLKD VDD_QREFD VDD_QCLKE VDD_SPI VDD_CP2 VDD_LCV VDD_QREFC VDD_QCLKC VDD_LCF VDD_QCLKA VDD_QREFA VDD3...

Page 3: ...y and high frequency noise To minimize ESR between power pins and the bypass capacitors Renesas suggests at least one bypass cap per power pin and to place these capacitors as close as possible to the power pins Thicker trace widths between the bypass capacitor and power pin can also help reduce the ESR Figure 2 Example of a 100nF Bypass Capacitor Frequency Response Figure 3 Example of a 10nF Bypa...

Page 4: ...0100 Rev 1 0 Page 4 Jun 3 2021 8V19N49x Hardware Design Guide Figure 4 Example of Larger Value 4 7uF Bypass Capacitor Frequency Response Figure 5 Example of Smaller Value 100pF Bypass Capacitor Frequency Response ...

Page 5: ...e For the VDDO output supplies to reduce output frequency interference the power rails between the output banks that operate at different output frequencies can be isolated using separate LDOs or using 1 to 2 ohm resistors if they share the same power source Additional smaller value capacitors e g 100pF in parallel with the existing 0 1uF near the power pins can provide additional higher frequency...

Page 6: ...fc fz recommend α to be greater than 3 fz is frequency at zero 4 Calculate Cp Where fp is frequency at pole β is ratio between frequency at pole and loop bandwidth β fp fc recommend β greater than 3 5 Verify maximum Phase Margin PM Where The PM should be greater than 50 degrees 3 2 3rd Order Loop Filter This section provides design guidelines for a 3rd order loop filter A typical 3rd order loop fi...

Page 7: ...tool will provide the component values Rs Cs and Cp as result The tool will also calculate maximum phase margin for verification The 3rd order loop filter R3 and C3 are also calculated using the actual 2nd order loop filter components values 3 3 Loop Filter Calculation Examples 3 3 1 Loop Filter for VCXO PLL 3 3 1 1 Second Order Loop Filter for the VCXO PLL This section provides calculation exampl...

Page 8: ...und or derived from the VCXO datasheet The VCO gain can also be measured from lab experiments In this example we use Kvco 10kHz V The 8V19N490 charge pump current can be programmed from 50uA to 1 6mA In this example assume the charge pump current is programmed to Icp 800uA Cs can be calculated from the following equation For α 8 Cs is calculated to be 0 99uF Cs greater than this value can be used ...

Page 9: ...e calculated using the following equation 2 Pick γ 4 in this example C3 is calculated to be 4 37nF A closest standard capacitor value can be used Table 2 shows some VCXO PLL Loop Filter examples for different VCXO frequencies Other values can also be used to meet other specific conditions and requirements Table 2 Loop Filter Examples VCXO Frequency 1 122 88MHz 30 72MHz VCXO Made Model Examples Eps...

Page 10: ...l VCO 2nd order loop filter works in conjunction with the internal circuitries A traditional loop filter calculation method may not be accurate After simulation and actual experiment an example of external two pole loop filter value is provided in Table 3 R3 51k Ohm 1 8k Ohm C3 4 7nF 33nF 1 Other VCXO frequencies can also be used with proper loop filter and parameter setting Below are examples of ...

Page 11: ...nput driven by a differential driver with AC coupling This section discusses only few examples other termination topologies can also be used if desired Figure 13 Input Termination Example 8V19N490 Reference Clock Input CLK nCLK Driven by a 3 3V LVPECL Driver Table 3 VCO PLL 2nd Order Loop Filter Recommendation VCXO used in the 1st PLL 122 88MHz 30 72MHz PDF Phase detector input frequency with doub...

Page 12: ...k Input CLK nCLK AC Coupling Termination Example 1 Figure 16 8V19N490 Reference Clock Input CLK nCLK AC Coupling Termination Example 2 VCC 3 3V Zo 50 Zo 50 LVDS Driv er VCC 3 3V R1 100 Clock Input CLK nCLK VCC 3 3V Clock Input CLK nCLK R4 10K R2 10K R3 5 1K R1 5 1K VCC 3 3V C1 C2 Differential Signal Zo Zo R5 2 x Zo VCC 3 3V Clock Input CLK nCLK C1 C2 Differential Signal Zo Zo R5 Zo R4 10K R3 5 1K ...

Page 13: ...esistor for the DC current path in order for the output to switch A standard LVPECL driver termination is displayed in Figure 17 There are many ways to terminate the LVEPCL driver Figure 18 to Figure 21 show several examples of LVPECL style driver termination Figure 17 Standard LVEPCL 750mV Driver Termination Figure 18 LVPECL 750mV Termination Example 1 VCC 3 3V High Input Impedance CLK nCLK R4 50...

Page 14: ...PECL Driver AC Coupling Termination for the Receiver with Built in Termination VCC 3 3V R4 50 R2 50 Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 50 C1 0 1uF optional High Input Impedance CLK nCLK 50 Ohm 50 Ohm 8V79S680 IN nIN VT VCC 3 3V Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 120 to 240 R1 120 to 240 Zo 50 Zo 50 VCC 3 3V LVPECL Driv er R2 120 to 240 R1 120 to 240 50 Ohm 50 Ohm 8V79S680 IN nIN VT VCC 3 3...

Page 15: ...e not quite same as standard LVPECL or LVDS The amplitude can be programmed to different amplitude levels 250mV 500mV 750mV and 1000mV The DC offset is about 2V for both LVPECL and LVDS driver 2V DC offset is close the standard LVPECL signal however 8V19N490 LVDS DC offset is about 2V which is not standard In some applications the receiver requires lower DC offset level with DC coupling interface ...

Page 16: ...e s ig n file U N N A M E D 0 TL N D e s ig n e r M in g L im H y p e rL y n x V 7 7 D a te Th u rs d a y S e p 1 1 2 0 0 8 Tim e 1 1 5 0 3 9 C u rs o r 1 V o lta g e 1 3 9 1 6 V Tim e 2 4 9 1 n s C u rs o r 2 V o lta g e 8 5 5 4 m V Tim e 6 9 8 2 n s D e lta V o lta g e 5 3 6 1 m V D e lta Tim e 4 4 9 1 n s S h o w L a te s t W a ve fo rm Y E S 4 0 0 0 6 0 0 0 8 0 0 0 1 0 0 0 0 1 2 0 0 0 1 4 0 0 ...

Page 17: ...n for the non built in is not feasible The DC coupling interface example to shift down the DC offset level is displayed in Figure 27 Figure 26 Receiver with Built in 100 ohm Figure 27 DC Coupling Example for Receiver with Built in Termination Figure 28 Simulation Waveform at the Receiver 50 Ohm R4 100 50 Ohm 8V19N490 LVEPCL 750mV 3 3V R1 43 100 R2 43 R3 100 Receiver w ith Built in 100 Ohm across ...

Page 18: ...d to shift close to this level Figure 29 Interface to Receiver with Built in Termination and Built in DC Bias The value of the component is shown in Table 4 VDDO 3 3V The QREF output is set to LVPECL style driver and the amplitude is set to 750mV Figure 30 Simulation Waveform at the Receiver Table 4 Component Values Component References Component Values R1 100 Ohm R2 100 Ohm R3 100 Ohm R4 100 Ohm ...

Page 19: ...021 8V19N49x Hardware Design Guide 5 Schematic Diagrams The following schematic diagrams are available from request 8V19N490 EVB schematic 8V19N490 EVB board layout 6 Revision History Revision Date Description 1 0 Jun 3 2021 Initial release ...

Page 20: ...re intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing your application and 3 ensuring your application meets applicable standards and any other safety security or other requirements These resources are subject to change without notice Renesas grants yo...

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