IDT SMBus Interfaces
PES24T3G2 User Manual
5 - 16
February 22, 2012
Notes
The format of the CMD field is shown in Figure 5.7 and described in Table 5.14.
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
3
EEADDR
Serial EEPROM Address. This field specifies the address of the Serial EEPROM
on the Master SMBus when the USA bit is set in the CMD field. Bit zero must be
zero and thus the 7-bit address must be left justified.
4
ADDRL
Address Low. Lower 8-bits of the Serial EEPROM byte to access.
5
ADDRU
Address Upper. Upper 8-bits of the Serial EEPROM byte to access.
6
DATA
Data. Serial EEPROM value read or to be written.
Bit
Field
Name
Type
1
Description
0
OP
RW
Serial EEPROM Operation. This field encodes the serial EEPROM oper-
ation to be performed.
0 - Serial EEPROM write
1 - Serial EEPROM read
1
USA
RW
Use Specified Address. When this bit is set the serial EEPROM SMBus
address specified in the EEADDR is used instead of that specified in the
ADDR field in the EEPROMINTF register.
When this bit is set the serial EEPROM SMBus address specified in the
EEADDR is used instead of that specified in the MSMBADDR field in the
SMBUSSTS register.
2
Reserved
Reserved
3
NAERR
RC
No Acknowledge Error. This bit is set if an unexpected NACK is observed
during a master SMBus transaction when accessing the serial EEPROM.
This bit has the same function as the NAERR bit in the SMBUSSTS reg-
ister.
The setting of this bit may indicate the following: that the addressed
device does not exist on the SMBus (i.e., addressing error), data is
unavailable or the device is busy, an invalid command was detected by
the slave, invalid data was detected by the slave.
4
LAERR
RC
Lost Arbitration Error. This bit is set if the master SMBus interface loses
16 consecutive arbitration attempts when accessing the serial EEPROM.
This bit has the same function as the LAERR bit in the SMBUSSTS reg-
ister.
Table 5.14 Serial EEPROM Read or Write CMD Field Description
Byte
Position
Field
Name
Description
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence (Part 2 of 2)
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
OP
USA
0
NAERR
LAERR
OTHERERR
0
Summary of Contents for 89HPES24T3G2ZBAL
Page 8: ...IDT PES24T3G2 User Manual 6 February 22 2012 Notes...
Page 12: ...IDT Table of Contents PES24T3G2 User Manual iv February 22 2012 Notes...
Page 14: ...IDT List of Tables PES24T3G2 User Manual vi February 22 2012 Notes...
Page 16: ...IDT List of Figures PES24T3G2 User Manual viii February 22 2012 Notes...
Page 20: ...IDT Register List PES24T3G2 User Manual xii February 22 2012 Notes...
Page 32: ...IDT PES24T3G2 Device Overview PES24T3G2 User Manual 1 12 February 22 2012 Notes...
Page 72: ...IDT SMBus Interfaces PES24T3G2 User Manual 5 20 February 22 2012 Notes...
Page 76: ...IDT Power Management PES24T3G2 User Manual 6 4 February 22 2012 Notes...
Page 156: ...IDT Configuration Registers PES24T3G2 User Manual 8 74 February 22 2012 Notes...