Renesas 89HPES24T3G2ZBAL, User Manual

Page: 54 / 165

IDT SMBus Interfaces
PES24T3G2 User Manual 5 - 2 February 22, 2012
Notes
tration. In some systems, this external SMBus master interface may be implemented using general purpose
I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these
systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 5.1(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus
multi-master arbitration is not required.
Master SMBus Interface
The master SMBus interface is used during a fundamental reset to load configuration values from an
optional serial EEPROM. It is also used to support optional I/O expanders used for hot-plug and other
status signals.
Initialization
Master SMBus initialization occurs during a fundamental reset (see Fundamental Reset on page 2-2).
During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode (MSMB-
SMODE) signal is examined. If this signal is asserted, then the Master SMBus Clock Prescalar (MSMBCP)
field in the SMBus Control (SMBUSCTL) register is initialized to support 100 KHz SMBus operation. If the
signal is negated, the MSMBCP field is initialized for 400 KHz SMBus operation.
Serial EEPROM
During a fundamental or hot reset, an optional serial EEPROM may be used to initialize any software
visible register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[2:0]) field
selects an operating mode that performs serial EEPROM initialization. The address used by the SMBus
interface to access the serial EEPROM is specified by the MSMBADDR[4:1] signals as shown in Table 5.1.
Note: MSMBADDR address pins are not available in the 19mm package. The MSMBADDR
address is hardwired to 0x50.
Device Initialization from a Serial EEPROM
During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES24T3G2. Any PES24T3G2
software visible register in any port may be initialized with values stored in the serial EEPROM. Each soft-
ware visible register in the PES24T3G2 has a CSR system address which is formed by adding the PCI
configuration space offset value of the register to the base address of the configuration space in which the
register is located. Configuration blocks stored in the serial EEPROM use this CSR system address shifted
right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system addresses and
not byte CSR system addresses).
Base addresses for the PCI configuration spaces in the PES24T3G2 are listed in Table 8.1, Base
Addresses for Port Configuration Space Register. Since configuration blocks are used to store only the
value of those registers that are initialized, a serial EEPROM much smaller than the total size of all of the
Address
Bit
Address Bit Value
1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
5 1
6 0
7 1
Table 5.1 Serial EEPROM SMBus Address