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BLOCK DIAGRAM

SHEET 2 OF 17

Tue Aug 01 17:54:15

2006

CR-2 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE2

89EBPES16T7

STGSCH-00083

B

J.CARRILLO

2006

B.OH

18-610-000

1.0

BLOCK DIAGRAM

5

8

3

8

7

7

6

6

5

4

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2

D

D

C

C

B

B

A

A

1

1

FAB P/N

REV.

SIZE

3

COPYRIGHT

(C) IDT

6024 SILVER

CREEK

VALLEY

RD. SAN JOSE,

CA 95138

CONFIDENTIAL

PROPERTY

OF INTEGRATED

DEVICE

TECHNILOGY,

INC.

CHECKED

BY

AUTHOR

DRAWING

NO.

TITLE

Summary of Contents for 18-610-000

Page 1: ...ilver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2007 Integrated Device Technology Inc IDT 89EBPES16T7 Evaluation Board Manual Eval Board 18 610 000 ...

Page 2: ...lure Analysis be performed LIFE SUPPORT POLICY Integrated Device Technology s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT 1 Life support devices or systems are devices or systems which a are intended for surgical implant in...

Page 3: ... 4 PCI Express Digital Power Voltage Converter 2 4 PCI Express Analog Power Voltage Converter 2 4 Core Logic Voltage Converter 2 4 3 3V I O Power Module 2 4 Power up Sequence 2 4 Required Jumpers 2 4 Reset 2 4 Fundamental Reset 2 5 Downstream Reset 2 5 Boot Configuration Vector 2 5 SMBus Interfaces 2 7 SMBus Slave Interface 2 7 SMBus Master Interface 2 9 JTAG Header 2 10 Attention Buttons 2 11 Mis...

Page 4: ...IDT Table of Contents EB16T7 Eval Board Manual ii March 30 2007 Notes ...

Page 5: ...Switches S5 S6 ON 0 OFF 1 2 6 Table 2 9 Slave SMBus Interface Connector 2 7 Table 2 10 SMBus Slave Interface Address Configuration 2 8 Table 2 11 PES16T7 SMBus Slave Interface Address Setting 2 8 Table 2 12 I O Expander 0 Bus Address 2 9 Table 2 13 I O Expander 1 Bus Address 2 9 Table 2 14 I O Expander 2 Bus Address 2 9 Table 2 15 I O Expander 4 Bus Address 2 10 Table 2 16 EEPROM SMBus Address Set...

Page 6: ...IDT Table of Contents EB16T7 Eval Board Manual iv March 30 2007 Notes ...

Page 7: ...Notes EB16T7 Eval Board Manual v March 30 2007 List of Figures Figure 1 1 Function Block Diagram of the EB16T7 Eval Board 1 1 Figure 2 1 SuperMicro X6DH8 G2 Motherboard 2 2 ...

Page 8: ...IDT List of Figures EB16T7 Eval Board Manual vi March 30 2007 Notes ...

Page 9: ...s The EB16T7 eval board is designed to function as an add on card to be plugged into a x8 PCIe slot available on a motherboard hosting an appropriate root complex microprocessor s and five downstream ports The EB16T7 is a vehicle to test and evaluate the functionality of the PES16T7 chip Customers can use this board to get a headstart on software development prior to the arrival of their own hardw...

Page 10: ...ot mode selection SMBUS Slave Interface 4 pin header SMBUS Master Interface connected to the Serial EEPROMs through I O expander Attention button for each downstream port to initiate a hot swap event on each port Four pin connector for optional external power supply Push button for Warm Reset Several LEDs to display status reset power Attention etc One 10 pin JTAG connector pitch 2 54 mm x 2 54 mm...

Page 11: ...l November 13 2006 In Tables 2 7 and 2 8 changed MSMSDDR to MSMBADDR and removed refer ences to P23MERGEN P45MERGEN and SWMODE 3 March 30 2007 In Figure 1 1 revised diagram to show a x4 connection from the PES16T7 device to the x4 downstream slot In Board Features section revised first line to clarify the board has one x8 port one x4 port and four x1 ports ...

Page 12: ...IDT Description of the EB16T7 Eval Board EB16T7 Eval Board Manual 1 4 March 30 2007 Notes ...

Page 13: ...ts The EB16T7 has five PCI Express downstream ports accessible through one x16 connector and four x1 connectors One specific port is capable of negotiating a x1 x2 or x4 link width and the remaining four ports are capable of negotiating a x1 link width All endpoint cards connected to the PES16T7 must support at least one of these link widths Basic requirements for the board to run are Host system ...

Page 14: ...hese clocks from a common source which is user selectable The common source can be either the host system s reference clock or the onboard clock generator Selection is made by stuffing resistors described in Table 2 1 Clock Configuration Stuffing Option Install Clock Source R36 R37 Onboard Reference Clock Use onboard clock generator R34 R35 Upstream Reference Clock Host system provides clock Defau...

Page 15: ...s of port 0 and port 1 The EB16T7 and all downstream ports are powered from the upstream port slot power If add in cards require more power than the upstream slot can support an external source is required to supply this extra power via an auxiliary 4 pin power connector on the board Only downstream ports 2 3 4 and 5 can be powered by this external power source through jumpers W45 W46 and W47 see ...

Page 16: ... and stabilize prior to applying the next voltage in the sequence to ensure internal latch up issues are avoided There are no maximum limitations to the time to valid power level requirements To insure that the sequencing requirements are met a 0 047µF is used at the SOFTSTART cap on the VTTPE s voltage converter U6 pin 36 in the EB16T7 Required Jumpers To deliver power to the PES16T7 switch the f...

Page 17: ...f the PES16T7 while power is on Downstream Reset The PES16T7 provides a a choice of either a software controlled reset for each downstream port through GPIO pins or a fundamental reset through PERST Selection is made by jumpers described in Table 2 6 Boot Configuration Vector A boot configuration vector consisting of the signals listed in Table 2 7 is sampled by the PES16T7 during a fundamental re...

Page 18: ...THALT Reset Halt When this signal is asserted during a PCI Express fundamental reset the PES16T7 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active This allows software to read and write registers internal to the device before normal device operation begins The device exits the reset state when the RSTHALT bit is cleared in the P0_SWCTL register thro...

Page 19: ...alization and the I O expander used for hot plug signals SMBus Slave Interface On the PES16T7 board the slave SMBus interface is accessible through the PCI Express edge connector as well as a 4 pin header as described in Table 2 9 Note The SMBus signals to the PCI Express edge connector is disabled by default To enable them place 0 ohm resistors at locations R202 and R203 A fixed slave SMBus addre...

Page 20: ... 2 SSMBUSADDR 2 3 SSMBUSADDR 3 4 0 5 SSMBUSADDR 5 6 1 7 1 Table 2 10 SMBus Slave Interface Address Configuration SMBUS Slave Interface Address Setting W40 SSMBADDR 5 W41 SSMBADDR 3 W42 SSMBADDR 2 W43 SSMBADDR 1 Slave Interface Bus Address OFF OFF OFF OFF 0b1110111 Default OFF OFF OFF ON 0b1110110 OFF OFF ON OFF 0b1110101 OFF OFF ON ON 0b1110100 OFF ON OFF OFF 0b1110011 OFF ON OFF ON 0b1110010 OFF ...

Page 21: ...s Address ON ON ON 0b0100000 Default ON ON OFF 0b0100001 ON OFF ON 0b0100010 ON OFF OFF 0b0100011 OFF ON ON 0b0100100 OFF ON OFF 0b0100101 OFF OFF ON 0b0100110 OFF OFF OFF 0b0100111 Table 2 12 I O Expander 0 Bus Address I O Expander 1 W2 W5 W8 Bus Address ON ON OFF 0b0100001 Default ON ON ON 0b0100000 ON OFF ON 0b0100010 ON OFF OFF 0b0100011 OFF ON ON 0b0100100 OFF ON OFF 0b0100101 OFF OFF ON 0b01...

Page 22: ...b0100110 OFF OFF OFF 0b0100111 I O Expander 4 W31 w44 w29 Bus Address OFF ON ON 0b0100100 Default ON ON ON 0b0100000 ON ON OFF 0b0100001 ON OFF ON 0b0100010 ON OFF OFF 0b0100011 OFF ON OFF 0b0100101 OFF OFF ON 0b0100110 OFF OFF OFF 0b0100111 Table 2 15 I O Expander 4 Bus Address W39 S5 8 S5 7 S5 6 Bus Address OFF OFF OFF OFF 0b0101 1111 OFF OFF OFF ON 0b0101 1110 OFF OFF ON OFF 0b0101 1101 OFF OFF...

Page 23: ...on Button Table 2 18 Attention Buttons Miscellaneous Jumpers Headers Ref Designator Type Default Description W45 W47 Header 1 2 Shunted 1 2 12 0V source from Upstream Port Default 2 3 12 0V source from external power connector W48 W51 Header Shunted Bypass hot plug controller Enable REFCLK to downstream ports Default W12 Header Shunted Disable EEPROM Write protect feature Default W4 W7 W11 W2 W5 W...

Page 24: ...urce from hot plug controller W21 Header 2 3 Shunted 2 3 Port 6 12V source base on W45 W47 Default 1 2 Port 6 12V source from hot plug controller W28 Header 2 3 Shunted 2 3 Port 5 12V source base on W45 W47 Default 1 2 Port 5 12V source from hot plug controller W33 Header 2 3 Shunted 2 3 Port 4 12V source base on W45 W47 Default 1 2 Port 4 12V source from hot plug controller W36 Header 2 3 Shunted...

Page 25: ...ator DS8 Green Port 2 Power Indicator DS6 Yellow Port 2 Attention Indicator DS13 Red Hot Plug Controller1 Power Fault Indicator DS16 Red Hot Plug Controller2 Power Fault Indicator DS2 Green Board Power Indicator 3 3V DS1 Red Board Reset Indicator DS17 Green Port 6 link up status output DS18 Green Port 6 active status output DS19 Green Port 5 link up status output DS20 Green Port 5 active status ou...

Page 26: ...FCLK REFCLK Reference clock 14 PETp0 Transmitter differential REFCLK differential pair 15 PETn0 pair Lane 0 GND Ground 16 GND Ground PERp0 Receiver differential 17 PRSNT2 Hot Plug presence detect PERn0 pair Lane 0 18 GND Ground GND Ground 19 PETp1 Transmitter differential RSVD Reserved 20 PETn1 pair Lane 1 GND Ground 21 GND Ground PERp1 Receiver differential 22 GND Ground PERn1 pair Lane 1 23 PETp...

Page 27: ...d 50 PETp8 Transmitter differential RSVD Reserved 51 PETn8 pair Lane 8 GND Ground 52 GND Ground PERp8 Receiver differential 53 GND Ground PERn8 pair Lane 8 54 PETp9 Transmitter differential GND Ground 55 PETn9 pair Lane 9 GND Ground 56 GND Ground PERp9 Receiver differential 57 GND Ground PERn9 pair Lane 9 58 PETp10 Transmitter differential GND Ground 59 PETn10 pair Lane 10 GND Ground 60 GND Ground...

Page 28: ...T7 are electronically connected in either a x4 configuration port 6 or a x1 configuration ports 2 3 4 and 5 According to the PCI Express specification the PRSNT1 pin should be wired to the farthest available PRSNT2 pin on the connector In the EB16T7 all PRSNT2 pins are tied together This allows the board to be installed in a x1 or a x4 slot via a slot reducer Locations of Connectors Jumpers and Sw...

Page 29: ... a configuration file into an EEPROM programmable data structure This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES16T7 and then to populate that EEPROM onto the Evaluation Board It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package The front end of the Device Management So...

Page 30: ...IDT Software for the EB16T7 Eval Board EB16T7 Eval Board Manual 3 2 March 30 2007 Notes ...

Page 31: ...Notes EB16T7 Eval Board Manual 4 1 March 30 2007 Chapter 4 Schematics Schematics ...

Page 32: ...R CLOCKS 1 SHEET 12 11 LINK STATUS WAKE PES16T7 SMBUS REFCLKS PES16T7 POWER 3 16 17 SHEET 1 OF 17 Wed Nov 08 13 10 27 2006 CR 1 MEB16T7_LIB MEB16T7 SCH_1 PAGE1 B 89EBPES16T7 18 610 000 1 0 B OH STGSCH 00083 2006 J CARRILLO STGC 0082R01 1 0 INTIAL RELEASE 2006 08 01 J CARRILLO 5 FAB P N 7 3 CHANGE BY REVISIONS CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY INC 6024 SILVER CREEK VALLEY RD SAN...

Page 33: ...EBPES16T7 STGSCH 00083 B J CARRILLO 2006 B OH 18 610 000 1 0 BLOCK DIAGRAM 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY INC CHECKED BY AUTHOR DRAWING NO TITLE ...

Page 34: ...21K 1 0 015UF 16V 10UF 1 2K 1 2K 499 1 25V 22UF 1 499 47UF 10V 10V 220UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF GRN 0 1UF 0 1UF 0 1UF RED 5 330 M_PERSTN POWER SUPPLY AND RESET 1 0 015UF 10K 0 1UF 0 1UF 3 14 3 14 16 13 12 11 10 9 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY...

Page 35: ...0 11 12 13 5 14 16 9 11 12 14 14 B_REFCLKP B_REFCLKN 5 F_REFCLKP F_REFCLKN E_REFCLKN E_REFCLKP 0 1UF 0 1UF 5 0 1UF 5 1 49 9 5 49 9 1 1 49 9 49 9 5 5 5 M_REFCLK1P M_REFCLK2P 16V 0 1UF 49 9 1 D_REFCLKP D_REFCLKN 49 9 1 1 1 1 49 9 C_REFCLKP 1 49 9 33 1 C_REFCLKN 49 9 1 1 49 9 49 9 1 49 9 33 33 475 0 1UF 33 5 5 5 5 33 M_REFCLK2N M_REFCLK1N 5 33 0 1UF 0 1UF 16V 1UF 1 5 33 33 33 33 33 33 10K 5 10K DNP 1...

Page 36: ...4 16 4 10 11 12 13 5 16 17 5 5 16 5 16 17 5 16 17 5 5 5 PBAIN JTAG_RST 5 10K 10K 5 PEAPN PDAPN S S 5 10K PBINTRLCK PBMRLN PBPIN PBPEP PBPDN PBPFN PBAPN PBAIN M_SDA M_SCL M_GPIO4 10K 5 2 7K 2 7K PEINTRLCK PEMRLN PEPDN PEPFN PEAPN PEAIN PEPIN PEPEP PDINTRLCK PDPEP PDPIN PDAIN PDMRLN PDPFN PDPDN PDAPN PCINTRLCK PCPEP PCPIN PCAIN PCMRLN PCPFN PCPDN PCAPN PFPFN PFPDN PFAPN M_SDA M_GPIO2 2 7K 2 7K M_SDA...

Page 37: ...3V_DS 0 012 2 0 022UF 0 1UF 5 0 1UF 5 10K 5 10K 5 10K 10K 5 5 10K 10K 5 10K 5 5 10K 0 1UF 0 1UF DNP DNP 0 022UF RED 0 01UF 0 01UF 23 2K 1 1 110K 0 0 0 0 0 0 5 10K 10K 5 5 10K GRN GRN 330 5 5 330 5 330 B_PCIE_12V B_PCIE_3_3AUX B_PCIE_3_3V C_PCIE_12V C_PCIE_3_3V PBC_INTN PB_PWRGDN PC_PWRGDN PCPEP PBPEP PCPFN PBPFN PC_PWRGDN PB_PWRGDN PBC_INTN 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV...

Page 38: ...UF 2 0 02 0 022UF 6800PF 0 012 2 15 5 0 1UF 5 10K 5 10K 5 10K 5 10K 5 10K 5 10K 5 10K 5 10K 0 1UF 0 1UF DNP DNP 0 0 0 0 0 0 110K 1 23 2K 1 0 01UF 0 01UF 10K 5 10K 5 10K 5 GRN RED GRN 5 330 5 330 5 330 HOT PLUG CONTROL PORT D E D_PCIE_12V D_PCIE_3_3AUX D_PCIE_3_3V E_PCIE_12V E_PCIE_3_3V E_PCIE_3_3AUX PDE_INTN PEPEP PDPEP PEPFN PDPFN PE_PWRGDN PD_PWRGDN 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 ...

Page 39: ... 0 0 DNP 0 1UF 0 1UF 10K 5 10K 5 10K 5 10K 5 0 1UF 2 0 022UF 0 1UF 5 15 6800PF 0 022UF 2 0 02 15 12V_DS 0 012 HOT PLUG CONTROL PORT F F_PCIE_3_3V F_PCIE_12V F_PCIE_3_3AUX 5 3_3V_DS F_PCIE_3_3AUX F_PCIE_12V F_PCIE_3_3V 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY I...

Page 40: ...0UF 5 330 GRN 16V 10UF 330 GRN B_12V 0 0 0 0 5 1K 5 B_3_3V M_B_PERST B_PERST PB_ACTIVEN PB_LINKUPN B_PERP2 B_PERST B_PERN1 B_REFCLKN B_PETN3 B_PETN1 B_PETP1 B_PETN0 B_WAKE M_SSMBDATA PBPDN B_PCIE_3_3AUX 11 11 12 12 13 13 13 13 11 11 10 10 9 9 9 9 9 9 9 9 9 9 9 9 9 9 16 13 12 11 10 3 6 16 9 17 17 9 9 4 6 9 9 9 9 9 9 9 9 17 13 12 11 10 4 16 14 5 13 12 11 10 4 16 5 5 6 9 0 1UF 5 8 3 8 7 7 6 6 5 4 4 2...

Page 41: ...30 5 GRN 5 330 GRN 0 0 C_12V 0 0 0 12V_DS C_PCIE_3_3AUX 5 5 1K PORT C CONNECTOR M_PERSTN C_PERST C_3_3V C_PCIE_3_3V M_C_PERST PC_ACTIVEN PC_LINKUPN C_REFCLKN C_PERST C_PERP0 C_PERN0 C_REFCLKP C_WAKE C_PETP0 C_PETN0 M_SSMBCLK M_SSMBDATA C_12V C_PCIE_3_3AUX PCPDN 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIA...

Page 42: ...CLK D_12V D_WAKE D_REFCLKN D_REFCLKP D_PERST D_PERP0 D_PERN0 PD_LINKUPN D_PERST M_PERSTN PD_ACTIVEN D_PCIE_3_3V D_3_3V PORT D CONNECTOR 5 1K 5 D_PCIE_3_3AUX 12V_DS 0 0 0 0 D_12V 0 GRN 5 330 GRN 330 5 10UF 16V 10UF 16V D_PCIE_3_3V D_3_3V M_D_PERST 0 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PROPERTY OF...

Page 43: ... 10UF 16V 10UF 16V 5 330 GRN 5 330 GRN E_12V 12V_DS 0 0 0 0 5 5 1K E_PCIE_3_3AUX PORT E CONNECTOR E_3_3V E_PCIE_3_3V PE_ACTIVEN M_PERSTN M_E_PERST E_PERST E_PERP0 E_PERN0 E_PERST PE_LINKUPN M_SSMBCLK E_12V E_WAKE E_PETN0 E_PETP0 M_SSMBDATA PEPDN E_PCIE_3_3AUX 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL ...

Page 44: ..._PETP0 F_PERN0 F_PERP0 F_REFCLKN F_REFCLKP F_PERST F_PCIE_3_3V F_3_3V F_3_3V F_PCIE_3_3V M_F_PERST F_PERST PF_ACTIVEN PF_LINKUPN PORT F CONNECTOR 3_3V_DS 0 0 10UF 16V 10UF 16V 5 330 GRN 5 330 GRN E_12V 12V_DS 0 0 0 5 5 1K M_PERSTN M_SSMBCLK E_12V M_SSMBDATA 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PR...

Page 45: ...TP1 U_PETP0 U_PETP7 U_PETP4 U_PETN2 U_PETN1 U_PETN0 U_PETN6 U_PETN7 U_PETN4 U_PETN3 U_PETN3 PERST U_PETN4 U_PETP6 U_PETP0 U_PETN1 U_PETP1 U_PETN2 U_PETP2 U_PETP3 U_PETN7 U_PETP7 U_PETN0 U_PETP4 U_PETN5 U_PETP5 U_PETN6 U_PERN7 U_PERP7 U_PERP6 U_PERN6 U_PERP5 U_WAKE U_PERP1 U_PERN1 U_PERN2 U_PERP2 U_PERN3 U_PERP4 U_PERP3 U_PERN5 U_PERN4 PA_ACTIVEN U_PERN0 U_PERP0 M_SSMBDATA M_SSMBCLK PA_LINKUPN 5 8 ...

Page 46: ...F 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 47UF 10V 47UF 10V 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 10V 47UF 47UF 10V 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 16V 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 16V 1UF PES16T7 POWE...

Page 47: ... M_RSTHALT M_SWMODE2 M_SWMODE1 M_SWMODE0 M_P01MERGEN 52R 567 000 89HPES16T7ZBBXG M_MSMBADDR3 M_MSMBADDR2 M_MSMBADDR1 M_MSMBADDR0 M_SCL M_SDA M_MSMBSMODE M_SSMBCLK M_SSMBDATA M_TCK M_TDI M_TDO M_TMS JTAG_RST M_C_PERST M_GPIO4 M_GPIO3 M_GPIO2 52R 567 000 89HPES16T7ZBBXG 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONF...

Page 48: ...AKE LINK STATUS WAKE 5 5 5 5 10K 0 0 5 10K 5 PE_LINKUPN PF_LINKUPN PD_LINKUPN PC_LINKUPN PB_LINKUPN 5 8 3 8 7 7 6 6 5 4 4 2 2 D D C C B B A A 1 1 FAB P N REV SIZE 3 COPYRIGHT C IDT 6024 SILVER CREEK VALLEY RD SAN JOSE CA 95138 CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY INC CHECKED BY AUTHOR DRAWING NO TITLE IN SN74LVC1G125 VCC Y GND A OE 3_3VAUX IN SN74LVC1G125 VCC Y GND A OE 3_3VAUX 3_...

Page 49: ...ual control of the On the bottom side of the board Rework Description or Action Required STG Release Effective Date Originator s Approval 89EBPES16T7 McKinley Eval Bd STG ECN STG DCN 18 610 000 N A 1 Connect wire from R242 left side non 3 3V side to R111 bottom of On the top side of the board 2 Remove R214 Copy Distribution Disposition of Existing Material Ben Hinson Brian Oh Robert Yang Dave Winn...

Page 50: ...re intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing your application and 3 ensuring your application meets applicable standards and any other safety security or other requirements These resources are subject to change without notice Renesas grants yo...

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