Reflex PLDA XpressGX5LP-QE Reference Manual Download

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XpressGX5LP-QE

Reference Manual

ustom

mbedded

ystems

Summary of Contents for PLDA XpressGX5LP-QE

Page 1: ...s com www reflexces com ReFLEXCESNorthAmerica AsiaPac Japan Phone 1 408 8875981 ReFLEXCESEurope Phone 33 0 169870255 Version 2 0 0 November 2015 Copyright ReFLEX CES 2015 XpressGX5LP QE Reference Manu...

Page 2: ...eFLEX CES in good faith This document is provided as is with no warranties whatsoever including any warranty of merchantability non infringement fitness for any particular purpose or any warranty othe...

Page 3: ...ayout 9 2 2 Block Diagram of the Board 10 2 3 Board Features 11 2 4 Mechanical Description 12 Chapter 3 XpressGX5LP QE Features 13 3 1 Stratix V GX FPGA Device 13 3 2 Board Configuration Module 13 3 3...

Page 4: ...e 8 Transceiver clock tree pin assignment 20 Table 9 Pin assignments for the PCI Express endpoint connector 21 Table 10 DDR3L SDRAM pin assignments 24 Table 11 QSFP 1 pin assignments 30 Table 12 QSFP...

Page 5: ...Figure 6 Max II EPM 570 board configuration module 14 Figure 7 Max II board manager 17 Figure 8 Reference Clock inputs 20 Figure 9 PCI Express connector 21 Figure 10 DDR3L SDRAM 24 Figure 11 QSFP int...

Page 6: ...ification Revision 2 0 Feedback and Contact Information Feedback about this document ReFLEX CES welcomes comments and suggestions about this documentation Please contact ReFLEX CES Technical Support a...

Page 7: ...G 10G Ethernet or any high speed link via QSFP to SPF splitter cable or up to two 40Gbs links Board configuration module Power monitoring Power Up and reset controller IP protection ReFLEX CES Protoco...

Page 8: ...scription of board features can be found in Section 2 3 1 3 System Requirements To use XpressGX5LP QE board features you must install the ReFLEX CES Software Tools The ReFLEX CES Software Tools can be...

Page 9: ...These voltages are available on the mezzanine power supply daughter card which is mounted on the XpressGX5LP QE by default This daughter card is supplied with the XpressGX5LP QE board See Section 3 1...

Page 10: ...XpressGX5LP QE Reference Manual 10 2 2 Block Diagram of the Board The XpressGX5LP QE board is based on an Altera Stratix V GX FPGA as shown below Figure 2 XpressGX5LP QE block diagram...

Page 11: ...bit wide chips which feature Section 3 7 QSFP interfaces Two QSPF interfaces connected to eight FPGA transceivers to enable 2 x 40Gbs links or up to 8 x 10Gbs links All links have the same reference c...

Page 12: ...ion The following diagram illustrates the mechanical architecture of the XpressGX5LP QE board without the fansink mounted Note The overall height of the board that is the height of the highest compone...

Page 13: ...0F100 Max II CPLD as a 32 bit FPP Configuration Module The FPP module consists of 2 x 256MB PC28F00BP30 Micron 16 bit FlashPROMs that are directly connected to the FPGA on the FPP 32 bit interface At...

Page 14: ...e shows pin assignments for the FlashPROMs on the FPGA Flash Data Flash Address Flash Control flash_data00 AP33 flash_ad00 AM28 flash_oe0 AT24 flash_data01 AT33 flash_ad01 AL27 flash_rst0 AV23 flash_d...

Page 15: ...lash_data18 AH33 flash_ad18 AP28 flash_data19 AL33 flash_ad19 AT26 flash_data20 AK33 flash_ad20 AJ29 flash_data21 AK32 flash_ad21 AL28 flash_data22 AJ32 flash_ad22 AW25 flash_data23 AH31 flash_ad23 AR...

Page 16: ...K2 max_leduser2 C10 flash_ad08 H7 flash_we0 A6 dclk_cpld A8 flash_ad09 H4 clrconfig A9 conf_rfu0 G9 AV22 flash_ad10 G3 flash_adv1 C2 nstatus G10 conf_rfu1 D9 AR24 flash_ad11 F2 flash_wp1 D1 conf_done...

Page 17: ...nt signals on the CPLD and other components Signal CPLD Pin FPGA or Component Pin Comment Protocore osc_config_proto E10 Na MAX Main clock input 50MHz proto_led0 B1 DSMAX3 Red LED MAX LEDs NDY proto_l...

Page 18: ...p MGT PCIe SMBU smb_temp_d K3 LM83 12 Temperature Data information inputs smb_temp_clk K4 LM83 14 temp_int J3 LM83 11 Heat sink command output Temperature critical warning temp_crit J4 LM83 16 pcie_sm...

Page 19: ...n AR8 AT8 LVDS 200 MHz CLK dedicated to DDR3L Bank0 Osc8 p n G7 G6 LVDS 200 MHz CLK dedicated to QDR2 banks Qsfp1_refclk0_p n AF6 AF5 LVDS 644 53125MHz or I C PLL clock for QSFP and extension interfa...

Page 20: ...either be a fixed 644 53125MHz 50ppm frequency or a user defined clock from an I C PLL Si570FBB0042DG The clock type can be selected via a signal coming from the FPGA Table 8 Transceiver clock tree pi...

Page 21: ...cification 2 0 and signals that appear bold are active signals implemented on the XpressGX5LP QE Side B Side A PCI Express Pin FPGA Pin Signal PCI Express Pin FPGA Pin Signal 1 12V 1 connected to mPRS...

Page 22: ...PETp3 30 RSVD 30 AL37 mPETn3 31 connected to mPRSNT 1 mPRSNT 2 31 GND 32 GND 32 RSVD 33 AH38 mPERp4 33 RSVD 34 AH39 mPERn4 34 GND 35 GND 35 AG36 mPETp4 36 GND 36 AG37 mPETn4 37 AF38 mPERp5 37 GND 38 A...

Page 23: ...eference Manual 48 connected to mPRSNT 1 mPRSNT 2 48 AA37 mPETn7 49 GND 49 GND Side B Side A PCI Express Pin FPGA Pin Signal PCI Express Pin FPGA Pin Signal Table 9 Pin assignments for the PCI Express...

Page 24: ...AR18 ddr3_Bank1_a01 E20 ddr3_Bank0_a02 AF16 ddr3_Bank1_a02 E23 ddr3_Bank0_a03 AM16 ddr3_Bank1_a03 A23 ddr3_Bank0_a04 AR19 ddr3_Bank1_a04 G20 ddr3_Bank0_a05 AG16 ddr3_Bank1_a05 F23 ddr3_Bank0_a06 AP19...

Page 25: ...5 ddr3_Bank1_d04 D24 ddr3_Bank0_d05 AG15 ddr3_Bank1_d05 F24 ddr3_Bank0_d06 AD16 ddr3_Bank1_d06 H25 ddr3_Bank0_d07 AC15 ddr3_Bank1_d07 G25 ddr3_Bank0_d08 AH19 ddr3_Bank1_d08 J25 ddr3_Bank0_d09 AJ18 ddr...

Page 26: ..._Bank0_d38 AB13 ddr3_Bank1_d38 G30 ddr3_Bank0_d39 AC14 ddr3_Bank1_d39 C30 ddr3_Bank0_d40 AV14 ddr3_Bank1_d40 N30 ddr3_Bank0_d41 AP13 ddr3_Bank1_d41 L30 ddr3_Bank0_d42 AV13 ddr3_Bank1_d42 R31 ddr3_Bank...

Page 27: ...qs00p AD15 ddr3_Bank1_dqs00p E24 ddr3_Bank0_dqs01n AG18 ddr3_Bank1_dqs01n R26 ddr3_Bank0_dqs01p AF19 ddr3_Bank1_dqs01p R25 ddr3_Bank0_dqs02n AG10 ddr3_Bank1_dqs02n F27 ddr3_Bank0_dqs02p AF10 ddr3_Bank...

Page 28: ...dr3_Bank1_tdqs03n U27 ddr3_Bank0_tdqs03p AN10 ddr3_Bank1_tdqs03p U26 ddr3_Bank0_tdqs04n AG13 ddr3_Bank1_tdqs04n A31 ddr3_Bank0_tdqs04p AF13 ddr3_Bank1_tdqs04p B31 ddr3_Bank0_tdqs05n AP12 ddr3_Bank1_td...

Page 29: ...The XpressGX5LP QE dual QSFP interfaces use eight FPGA GXB transceivers to enable either 2 x 40Gbps or up to 8 x 10Gpbs links Both QSFP interfaces are fully independent although they share a referenc...

Page 30: ...qsfp1_rx3p AM2 qsfp1_refclk0_n AF5 qsfp1_tx0n AU3 qsfp1_refclk0_p AF6 qsfp1_tx0p AU4 qsfp1_refclk1_n AD6 qsfp1_tx1n AR3 qsfp1_refclk1_p AD7 qsfp1_tx1p AR4 qsfp1_tx2n AN3 qsfp1_tx2p AN4 qsfp1_tx3n AL3...

Page 31: ...XpressGX5LP QE via a MicroBNC connector Samtec part MCS P P RA TH1 Figure 13 MicroBNC for time stamping Time stamping signals are available as following on the FPGA FPGA MicroBNC qsfp2_tx2n AA3 qsfp2_...

Page 32: ...s It also features 10 LVCMOS25 signals The connector part number is Samtec LSHM 130 01 F DH A S K and mates with Samtec HLCD cables or LSHM connectors Figure 14 Extension interface Signal FPGA Pin Com...

Page 33: ...t_link_rx4n P39 27 Ext_link_tx4p N36 30 Ext_link_rx4p P38 29 Ext_link_tx5n L37 34 Ext_link_rx5n M39 33 Ext_link_tx5p L36 36 Ext_link_rx5p M38 35 Ext_link_tx6n J37 40 Ext_link_rx6n K39 39 Ext_link_tx6p...

Page 34: ...able describes pin assignments for the LEDs Table 16 Pin assignments for the board LEDs Signal FPGA Pin LED Name LED Color user_led0 AJ20 DS2 Yellow user_led1 AK21 DS3 Yellow user_led2 AL20 DS4 Green...

Page 35: ...3 12 Local Reset One active low reset push button BPI is available on the solder side of the board to enable register initialization Figure 16 Reset button Signal FPGA Pin user_resetn N14 Table 17 Pi...

Page 36: ...EEPROMs Two 256k bit Serial FlashPROMs M24256BSMN6T are available on the solder side of the XpressGX5LP for data storage via two I C links The following table shows pin assignments for the EEPROMs Tab...

Page 37: ...available on the board for IP protection purposes It is reserved for future use The following table shows the PIC pin assignment on the FPGA Table 20 Pin assignments for the PIC pic_gpio0 AG26 pic_gpi...

Page 38: ...es are available on the mezzanine power supply daughter card which is mounted on the XpressGX5LP QE by default The PCI Express 12 V generates 1 5 V 1 8 V 2 5 V and 0 9 V voltages while the 3 3 V gener...

Page 39: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information ReFLEX CES XpressGX5 LPA7HE Gen3 XpressGX5 LPA4QE Gen3 XpressGX5 LPA7SE Gen3...

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