Redpine Signals, Inc. Proprietary and Confidential
1
Reference Schematics
The following is a reference circuit schematic of an Evaluation Board using RS-9110-N-11-02 WLAN Module. The schematics
show both SDIO and SPI Host Interface options. The layout corresponding to this schematic is also shown in this document
as a reference
1.1
SDIO Interface
C3
0.1uF
PSPI_CSN1
PSPI_MISO
PSPI_MOSI
PSPI_CLK
Microwave switch is used for evaluating
the standalone Transmit/Receive
performance of the WLAN module by
providing direct connectivity to Signal
generator/Analyzer through RF cable
D1
LED
U
A
R
T
2
_
IN
S
L
E
E
P
_
C
L
K
_
X
1
S
L
E
E
P
_
C
L
K
_
X
1
Z1 , Z2, Z3 form the tuning network
for matching the impedance of the
Antenna. The values depend upon
the layout. In case tuning network is
not implemented Z1 should be
placed as 8.2pF as default
XTAL_EN
Redpine Signals Confidential
C11
0.1uF
1
1
2
2
FB4
BEAD
VDD_EXT
C6
1uF
VRF33
1
1
2
2
FB2
BEAD
PSPI_MISO
GPIO_0
BT_PRIORITY
PSPI_MOSI
VIN33
SPI Serial Flash
NOTE::If required C7 can be increased to
22uF for further improving the Transmit
EVM
W
L
A
N
_
A
C
T
IV
E
B
T
_
A
C
T
IV
E
PSPI_CLK
CE#
1
SCK
6
SI
5
SO
2
VDD
8
HOLD
7
WP#
3
VSS
4
U3
SST25VF016B-75-4I-QAF-T
L1
4.7uH
VDD_EXT
C14
10uF
PSPI_CSN1
VDD_EXT
OPTIONAL
S
D
IO
_
D
A
T
A
0
DVDD33
VMOD
S
D
IO
_
C
M
D
S
D
IO
_
C
L
K
S
D
IO
_
D
A
T
A
3
C8
0.1uF
S
D
IO
_
D
A
T
A
2
S
D
IO
_
D
A
T
A
1
VRF33
Power Supply Filter Section
C10
0.1uF
Tantalum
R8
4.7K
Tantalum
1
1
2
2
FB3
BEAD
1
1
2
2
FB5
BEAD
Mating Connector Part No::MXHS83QH3000
C13
0.1uF
ANT1
1
ANT2
2
ANT1
ANT-2.45G
I2
C
_
S
D
A
ANTIN
3
ANTOUT
4
G
N
D
1
G
N
D
2
G
N
D
5
G
N
D
6
J2
MM8430-2610RA1
C5
8.2pF
I2
C
_
S
C
L
R3
820E
C
L
K
_
R
E
F
UART1_RTS
UART1_CTS
XTAL_IP_EN
GPIO_1
R
E
S
E
T
_
n
HOST_WAKEUP_INT
UART1_OUT
UART1_IN
UART2_OUT
VMOD
C4
10uF
802.11bgn WLAN Module
C12
22uF(CASE B)
VDD_EXT
C7
10uF(CASE B)
RESET_n
C9
0.1uF
VIN33
RESET Circuitry
R7
100K
CLK_REF
Make:: TXC
OE
1
GND
2
OUT
3
VDD
4
U1
7C40000192
C1
2.2uF
XTAL_EN
XTAL_EN
XTAL_EN
XTAL_EN
R1
33E
VRF28
1
1
2
2
FB1
BEAD
Reference Clock Circuitry
TP1
Place Z1-Z3 Close
together and near to
ANT1
SDIO_CLK
SDIO_DATA1
SDIO_DATA3
SDIO_DATA0
CD/DAT3
1
CMD
2
VSS1
3
VDD
4
CLK
5
VSS2
6
DAT0
7
DAT1
8
DAT2
9
J1
SDIO Interface Connector
SDIO_DATA2
SDIO_CMD
VIN33
C2
10uF
R25**
S
L
E
E
P
_
C
L
K
_
X
2
R25** value should be adjusted based
on driver output impedance and PCB
Trace Impedance,,(33E is Nominal)
T
D
O
R
6
1
K
Z1
TBD
Z3
TBD
DVDD33
Z2
TBD
Title
Size
Document Number
Rev
Date:
Sheet
of
<Doc>
RS9110-N-11-02 SDIO - Reference Schematics
Custom
2
2
Tuesday, September 20, 2011
R
5
1
K
50 Ohm RF line
CMS02
D2
R
4
1
K
Note:
Microwave coaxial
connector with switch
Rev6.1
Ver6.1
VRF28
RF Out Circuitry
AGND
56
RF_OUT
57
AGND
58
GND
25
N
C
1
DVDD33
17
P
S
P
I_
C
S
N
0
4
0
LED_ON
24
MODE_SEL_1
51
VRF28
52
XTAL_EN
23
R
E
F
_
C
L
K
1
4
PSPI_CSN1
46
S
L
E
E
P
_
C
L
K
_
X
1
3
5
S
L
E
E
P
_
C
L
K
_
X
2
3
4
I2
C
_
S
C
L
6
I2
C
_
S
D
A
7
GND
30
GND
26
R
E
S
E
T
n
1
5
N
C
4
1
W
L
A
N
_
A
C
T
IV
E
3
1
BT_PRIORITY
29
S
L
E
E
P
_
C
L
K
_
IN
3
2
HOST_WAKEUP_INT
53
N
C
4
2
V
R
F
3
3
4
3
V
R
F
3
3
4
4
S
D
IO
_
D
A
T
A
3
/S
D
3
1
3
S
D
IO
_
D
A
T
A
2
/S
P
I_
IN
T
R
1
2
S
D
IO
_
D
A
T
A
1
/S
P
I_
M
IS
O
1
1
S
D
IO
_
D
A
T
A
0
/S
P
I_
M
O
S
I
1
0
S
D
IO
_
C
M
D
/S
P
I_
C
S
9
S
D
IO
_
C
L
K
/S
P
I_
C
L
K
8
GPIO_1
55
G
N
D
1
6
VINBCKDC
27
V
IN
L
D
O
P
1
2
3
3
9
F
B
D
C
1
P
3
3
8
V
O
U
T
B
C
K
D
C
1
P
3
3
7
U
A
R
T
2
_
IN
3
6
UART1_RTS
22
UART1_CTS
21
UART1_OUT
18
UART1_IN
19
T
C
K
2
T
D
I
3
T
M
S
4
T
D
O
5
XTAL_EN_IP
54
GPIO_0
28
B
T
_
A
C
T
IV
E
3
3
UART2_OUT
20
PSPI_MISO
47
G
N
D
4
5
MODE_SEL_0
50
PSPI_CLK
49
PSPI_MOSI
48
U2
RS9110-N-11-02
Figure 1 SDIO Interface Integration
NOTE
: Pull up resistors should be present on SDIO CMD & SDIO Data lines according to the section 6.6.5 of SD physical layer
specification, version 2.00
