Direct Memory Access Controller (DMAC)
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Fig 9-12 shows a a burst transaction followed by a single transaction, followed by a burst transaction at the end of a block. After the first burst
transaction completes, the peripheral is in the Single Transaction Region and DMAC samples that dma_single[0] is asserted at T1. The
dma_req[0] signal is triggered in the middle of this single transaction at time T2. This burst transaction request is ignored and is not serviced.
An active edge on dma_req[0] is re-generated and sampled by DMAC at time T3. This burst transaction completes the block transfer using an
Early-Terminated Burst Transaction.
Fig 9-12 Burst transaction ignored during active single transaction
9.2.6.3.1
Generating dma_req and dma_single Hardware Handshaking Signals
Fig 9-13 illustrates a suggested method of generating dma_req and dma_single for a source peripheral when the peripheral is not the flow
controller. The single_flag signal in Fig 9-13 is asserted when the source FIFO has at least one source data item in the FIFO. The burst_flag signal
in Fig 9-13 is asserted when the source FIFO contains data items greater than or equal to some watermark-level number of data items in it.
Note
: Fig 9-13 shows dma_req and dma_single being de-asserted when dma_ack is asserted. It also shows how, once asserted, dma_req and
dma_single remain asserted until dma_ack is asserted. The example assumes active-high handshaking.
The destination peripheral dma_req and dma_single signals can be generated in a similar fashion, but in this case the single_flag signal in Fig 9-
13 is asserted when the destination FIFO has at least one free location. The burst_flag signal in Fig 9-13 is asserted when the destination FIFO
contains free locations greater than or equal to some watermark-level number.
Fig 9-13 Generation of dma_req and dma_single by source
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