Ameba-D User Manual
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176
Note
: The only allowed transitions between the rows of Table 9-19 are from any row into Row 1 or Row 5. As already stated, a transition into
row 1 or row 5 is used to terminate the DMA transfer; all other transitions between rows are not allowed. Software must ensure that illegal
transitions between rows do not occur between blocks of a multi-block transfer. For example, if block N is in row 10, then the only allowed
rows for block N +1 are rows are rows 10 or 5
.
9.4.4
Programing Example
The flow diagram in Fig 1-58 shows an overview of programming the DMA. This section explains the step-by-step programming of the DMAC.
The example demonstrates row 10 of Table 9-19 for Multi-Block Transfer with Linked List for Source and Linked List for Destination. This
example uses the DMAC to move four blocks of contiguous data from source to destination memory using the Linked List feature.
(1)
Set up the chain of Linked List items—otherwise known as block descriptors—in memory. Write the control information in the LLI.CTLx
register location of the block descriptor for each LLI in memory for Channel 1. In the LLI.CTLx register, the following is programmed:
a)
Set up the transfer type for a memory-to-memory transfer:
- ctlx[22:20] = 3'b000;
b)
Set up the transfer characteristics:
i.
Transfer width for the source in the SRC_TR_WIDTH field
ctlx[6:4] = 3'b001;
ii.
Transfer width for the destination in the DST_TR_WIDTH field
ctlx[3:1] = 3'b001;
iii.
Source master layer in the SMS field where the source resides
ctlx[26:25] = 2'b00;
iv.
Destination master layer in the DMS field where the destination resides
ctlx[24:23] = 2'b00;
v.
Incrementing address for the source in the SINC field
ctlx[10:9] = 2'b00;
vi.
Incrementing address for the destination in the DINC field
ctlx[8:7] = 2'b00;
(2)
Write the channel configuration information into the CFGx register for Channel 1:
a)
HS_SEL_SRC/HS_SEL_DST bits select which of the handshaking interfaces—hardware or software—is active for source requests on
this channel.
- cfgx[11] = 1'b0;
- cfgx[10] = 1'b0;
These settings are ignored because both the source and destination are memory types.
b)
If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the
source and destination peripheral by programming the SRC_PER and DEST_PER bits:
- cfgx[46:43] = 1'b0;
- cfgx[42:39] = 1'b0;
These settings are ignored because both the source and destination are memory types.
(3)
The following For loop, shown as a programming example, sets the following:
LLI.LLPx register locations of all LLI entries in memory (except the last) to non-zero and point to the base address of the next Linked
List Item
LLI.SARx/LLI.DARx register locations of all LLI entries I
n memory point to the start source/destination block address preceding
that LLI fetch
The For statement below configures the LLPx entries:
for(i=0 ; i < 4 ; i=i+1) begin
if (i == 3) llpx = 0; // end of LLI
else llpx = ll 20; // start of next LLI
//-: Program SAR
`AHB_MASTER.write(0, llp_addr, sarx, AhbWord32Attrb, handle[0]);
//-: Program DAR
`AHB_MASTER.write(0, (ll 4), darx, AhbWord32Attrb, handle[0]);
//-: Program LLP
`AHB_MASTER.write(0, (ll 8), llpx, AhbWord32Attrb, handle[0]);
//-: Program CTL
`AHB_MASTER.write(0, (ll 12), ctlx[31:0], AhbWord32Attrb, handle[0]);
`AHB_MASTER.write(0, (ll 16), ctlx[63:32], AhbWord32Attrb, handle[0]);
// update pointers
llp_addr = ll 20; // start of next LLI
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