8. Input/Output Interfacing
45
required for the RS232C interface is the installation of
a jumper wire in the C5 holes on the CDP18S601
Microboard. The pin connections for connectors J1
and J2 are shown in Table XII.
Serial data input is presented to either EF3 or EF4,
selectable by links as shown in Table XIII. UT62
requires the use of EF4. EF3 is made available for user
software. The serial interface is always selected and not
governed by the two-level I/O conventions.
Table X ll—Serial Interface Signals and Pin
Connections (J1 and J2)
M icroboard Com puter 20-mA Serial Interface
(J1)
Pin
Signal
Pin
Signai
2 NC
7
DATA OUT SOURCE
3 DATA OUT RETURN 8 DATA IN SOURCE
4 DATA IN RETURN 9 NC
5 NC
M icroboard Com puter EIA RS232C Serial Inter
face (J2)
Pin
Signal
1 GND
2 DATA IN
3 DATA OUT
4 NC
5 VACANT (KEY)
Pin
Signal
6 HIGH LEVEL
7 HIGH LEVEL
8 HIGH LEVEL
9 NC
10 GND
Table X lll—Llnk LK36 Selection Chart
Link LK36
7:10
8:9
Function
Data to EF3
Data to EF4
Parallel I/O Interfacing
The parallel I/O interface consists of 20 lines
provided on connector P2 of the CDP18S601. See
Table XIV for the pin connections and signal names.
These 20 lines are generated by the CDP1851
Programmable 1/ O Interface and may be programmed
as input, output, or bidirectional individually or as a
block. The P2 connector also provides the Q line, EF1
through EF4, CLEAR, three different voltages, and a
logic ground.
For more detailed information on the Program
mable I/ O Interface C D P 1851, refer to the data sheet
for that device (File No. 1056).
The CDP1851 is assigned to I/O group eight.
Therefore, in order to enable access, a 61 output
instruction with data = 08 is required before read,
write, or control I/O may be performed.
Signal ARDY conditioned by the group select
generates E F 1; BRDY and group select generates EF1.
Table XlV—Parallel I/O Interface Signals
and Pin Connections (P2)
Pin
Signal
Pin
Signal
1
B2-P
2
GND
3
B1-P
4
B3-P
5
B0-P
6
B4-P
7
BSTB-P
8
B5-P
9
BRDY-P
10
B6-P
11
AD7-P
12
B7-P
13
AD6-P
14
GND
15
AD5-P
16
CLEAR-N
17
AD4-P
18
GND
19
AD3-P
20
Q-P
21
AD2-P
22
GND
23
AD1-P
24
EF4-N
25
AD0-P
26
EF3-N
27
ASTB-P
28
GND
29
ARDY-P
30
+5V
31
EF2-N
32
-5V /-15V
33
EF1-N
34
+12V/+15V
BRDY and group select generates EF2. Pins A and B
of link LK41 may be jumpered if interrupt-driven
software is to be used. Then, INTA or INTB generates
INT unconditionally.
Once the group select is accomplished, N1 and N2
are used to address the CDP1851. The following read
and write instructions are used to access data, status,
and command registers.
62—Write to control register
64—Write to Port A data register (if A is an output)
66—Write to Port B data register (if B is an output)
6A—Read status register
6 C -R e a d Port A data register (if A is an input)
6E—Read Port B data register (if B is an output)
Using the READY Lines for
Data Synchronization
The Port A and Port B RDY lines are presented to
the CPU EF1 and EF2 lines when the group select is
set. Note that there is a logic reversal: when RDY is
true, the EF is false. A test for ARDY true might use
the B1 instruction (34) which would take the branch if
ARDY were false. Even though these RDY lines are
primarily intended for “handshaking” with the device
on the other end of the cable, they are useful for
synchronizing data transfer between the CDP 1851 and
the CPU.
When a port designated as an
output
port is loaded,
RDY goes true. When the receiving device takes the
data, it transmits STB which removes RDY. The
software can then test RDY until it is false (EF 1 or EF2
true), and load the next output byte. When a port is
designated as an
input
port, reading the data sets
RDY, and the transmitting device resets RDY when it
transmits data and STB. Again, the software tests to
see if RDY is false and then reads the input byte.
In this
case, a dummy read after reset is necessary to raise the
first RDY.
