Rastergraf
1-4 General Information
The Borealis design is based on technology licensed by Rastergraf from
S3/Number Nine. The chip itself is manufactured for Rastergraf by LSI
Logic using LSI’s .35u G-10P ASIC process.
The Borealis graphics controller is implemented using a highly pipelined
graphic processor architecture. This architecture allows for high
performance 2D and 3D rendering. After a sequence of commands and
parameters are written, the Borealis executes the selected command
without any further host processor intervention. A Display List Processor
enables the Borealis to repetitively execute strings of commands.
The Borealis supports a local frame buffer with up to 32 MB SGRAM
using a 128-bit wide data bus. The frame buffer may be accessed as linear
buffers through the frame buffer interface or through the drawing engine.
The large local buffer may be used as a display buffer, as well as off-
screen memory to be used for the storage and manipulation of bitmaps,
texture maps, Z buffering or fonts.
Figure 1-1 Borealis Block Diagram
Host Bus
Interface
CRT
Controller
Memory
Controller
PXD[127:0]
CJ[15:0]
BLANK
HSYNC
AD[31:0]
CAS
HBCLK
RST
CNTRL[6:0]
ADR[11:0]
WE
VSYNC
CRTclk
DQM[15:0]
SF
MCLK
Display
List
Processor
Linear
Controller
BE[3:0]
CS[0,2]
Internal
RAMDAC
Windows
RAS
PD[7:0]
PA[7:0]
DDC, DDA
RED
GREEN
BLUE
Engine
Drawing
2D/3D
VGA
