ArgusPMC Technical Overview
PMC (PCI) Bus
16 MB
Display
Memory
PLX
PCI6154
32/64 bit
33/66 MHz
PCI Bridge
Borealis
Graphics
Accelerator
Channel A
128
Quad
Image
BIOS
Control/Address
68-Pin Connector
Memory Data
16 MB
Display
Memory
Borealis
Graphics
Accelerator
Channel B
NEC
uPD720101
USB 2.0
Host
Controller
Conexant
Fusion 878A
Video Input
Processor
Channel A
Conexant
Fusion 878A
Video Input
Processor
Channel B
128
Control/Address
Memory Data
32 bit
66 MHz
32 bit
66 MHz
32 bit,
33 MHz
32 bit,
33 MHz
32/64 bit
PLX
PCI6150
32 bit
66/33 MHz
PCI Bridge
Graphics
Channel
A
VGA/DVI
Graphics
Channel
B
VGA/DVI
USB
Channels
1 & 2
Video
Input
Channel
A
Video
Input
Channel
B
Micronas
UAC3556B
USB Audio
CODEC
USB
Ch 4
Stereo Line I/O or Mono MIC
Audio
I/O
ArgusPMC Functional Diagram
page 3
Introduction
The Rastergraf ArgusPMC is a PMC (PCI Mezzanine Card) multifunc-
tion display controller. Referring to the block diagram, the Argus is
composed of six functional blocks: PMC interface bridge, secondary
PCI bridge, dual Borealis graphics controllers, USB 2.0 controller,
Stereo Audio Controller, and dual Fusion878A video digitizers.
Dual PCI Bridge Architecture
The PLX PCI6154 Asynchronous PCI Bridge supports all PMC inter-
faces, from 32-bit, 33 MHz to 64-bit, 66 MHz, while enabling the local
side to always operate at 32 bit, 66 MHz, which is the native interface
for the graphics controllers and secondary bridge. This capability is
due to the 6154’s use of large internal FIFOs to decouple the primary
and secondary PCI buses from each other.
A second bridge, a PLX PCI6150, is used to minimize the impact of
the slower (33 MHz PCI) digitizer and USB devices by decoupling
them from the primary 66 MHz local bus
Video Inputs
The Argus provides two Conexant Fusion 878A Video Digitizers, which
are single-chip solutions for NTSC and PAL composite video or S-
Video capture on the PCI bus. The 878A performs on-the-fly image
scaling and clipping. Its RISC-based high throughput DMA engine
transfers or CPU memory via the PCI bus.
128-Bit Graphics Accelerator
Each display channel is powered by a Borealis graphics accelerator.
With its 128-bit wide memory bus, the Borealis can draw up to sixteen
256-color pixels each memory cycle for a raw drawing speed of 2
GB/s. The drawing engine’s performance is further enhanced by its
display list capabililty, which enables it to execute lists of instructions
from the CPU, rather than just one at a time. The Borealis and the
host CPU can process data independently, thus breaking the lockstep
which often reduces system throughput.
The display memory has 16 MB of high speed SGRAM, which pro-
vides ample local storage for the graphics image and off-screen data
such as texture maps, Z-buffer, and backing store.
The Borealis uses a programmable Drawing Engine-based Look Up
Table (LUT) to provide YUV to RGB color space conversion. When
video data is copied from off-screen memory as part of the video
image double-buffering operation, pixels can be converted on the fly to
the current display pixel format. This allows for efficient use of off-
screen memory and the ability to dynamically accommodate a variety
of image formats.
The Borealis can smoothly X/Y scale small RGB or YUV video clips up
to full screen at any resolution and any color depth, and maintain a
rate greater than 30 frames per second.
For startup support on any system expecting a VGA device on power
up, the Argus graphics Channel A includes a quad image BIOS that
supports VGA and FCode, with or without Sync-On-Green (SOG).
Once the operating system is running, full function drivers can be
loaded, allowing the Borealis’s extended instruction set to be utilized.
The Borealis programmable video timing ranges from 30 to 150 Hz
vertical and 15.7 to 100 kHz horizontal refresh rates, with a pixel clock
up to 250 MHz, giving display formats up to 1920 x 1280 x 32 bpp.
The display output is directed through an internal RAMDAC which
includes a graphics cursor with a 64 x 64 x 2 bit map. It integrates the
graphics and cursor pixels into 24-bit color values (8 bits each of
RGB). The analog signals from the RAMDAC are connected to a stan-
dard RGBHV (VGA) or SOG monitor. Display Data Channel lines
enable the host computer to control the monitor. A separate 24-bit par-
allel port from the Borealis supports DVI output via a DVI encoder.
USB 2.0 and Stereo Audio Controllers
USB 2.0 supports data rates in excess of 400 Mbit/s, making it viable
for video input, external disk drives, and many other applications. USB
is also useful for mouse, trackball, keyboard, and scanner. The
ArgusPMC uses the NEC uPD720101 USB 2.0 host controller. As
used on the Argus, two channels are available for user connections
and one channel is connected to the Micronas UAC 3555B USB
Stereo controller (CODEC). Controlled by the CPU via a USB port, the
UAC3556B is intelligent subsystem supplies a low overhead, software
compatible, full function solution. It includes Mono MIC
or
Stereo Line-
In/Out, programmable 5-band equalizer, volume, balance, tone con-
trols, and dynamic range.
I/O Connections
All connections are made through the Argus front panel 68-pin high
density (HD) ribbon connector and available breakout cable. The stan-
dard breakout cable splits the functions into dual VGA, dual DVI, dual
USB 2.0, 3.5 mm Stereo In and Out/Mono MIN jacks, and dual S-
Video/2xVin Mini-DIN connectors.
