Jitter analysis and clock data recovery
R&S
®
RTO6
1115
User Manual 1801.6687.02 ─ 05
"Bandwidth"
Sets the PLL bandwidth. It defines the part of the spectrum that the
PLL can follow during synchronization. The PLL bandwidth is usually
defined by the transmission standard.
"Rel. band-
width"
Sets the relative bandwidth, that is the ratio of the nominal bit rate to
the PLL bandwidth.
Remote command:
Reverse lock
Available for "Algorithm" > "PLL".
Enables the reverse lock PLL algorithm. The signal is locked on the first edge.
Remote command:
Initial phase
Available for "Algorithm" > "PLL".
Defines the phase reference for the first clock edge.
"First sample"
The first clock edge matches the first sample of the waveform at the
left border of the display.
"First data
edge"
The first clock edge matches the first edge of the data signal.
Remote command:
Selected results
Available for "Algorithm" > "PLL".
The PLL requires some time to synchronize to the phase of the data stream. You can
select when the CDR algorithm returns clock edges:
"After initial
sync."
The clock edges of the synchronization time are discarded; results
are gathered after initial synchronization of the CDR. Thus, meaning-
ful TIE measurement results can be obtained.
"All"
All clock edges are used.
Remote command:
18.3.2
Hardware CDR (option R&S
RTO6-K13)
Hardware-based clock data recovery uses the digital CDR module to recover the clock
edges. The generated clock is acquired similar to a waveform and occupies an adja-
cent analog channel. If the source is CH1, the recovered clock blocks CH2, and vice
versa. CH3 and CH4 work in the same way. The occupied channel cannot be dis-
played, but the generated clock can be displayed as math waveform.
Clock data recovery
