Ramsey Electronics AR2WT, Manual

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AR2
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Block G. This is the main detector, AGC, 2nd LO, reference oscillator, and
filtering all wrapped into one part.
Block H. 2nd IF filtering. This section is for further attenuating adjacent
signals. The goal is to reduce signals 25kHz away more than 90dB, or the
range of the AGC of the detector component. Two cascaded 450kHz filters are
used here on top of the 10.7MHz ceramic filter.
Block I. After the AM has been detected the small level of audio signal is
amplified enough to drive a speaker to respectable volumes
Block J. The Phase Locked Loop works in conjunction with the VCO (NE602
and varactor diode) and the reference 10.25MHz oscillator. The PLL part (U2,
MC145170P2) has two dividers and some option registers for different designs
that are usually set only once. One of the two dividers divides down the LO
frequency from the VCO to make the channel step size 25kHz (N divider), and
the other divides down the reference oscillator to the specific channel step size
of 25kHz (C divider). The 25kHz is the reference comparator frequency, and
the output of the PLL tries to make the VCO tune so that the output of it
s divider is also “Locked” to 25kHz. A correction pulse is generated for each
phase of the reference, and that is where phase locked loop comes from!
For example the PLL is programmed by the microcontroller to have a C value
of 410. This means the reference clock of 10.25MHz is divided by 410 to give a
divider output of 25kHz. This value remains constant throughout the AR2
circuit. To receive 118.3MHz we have to set the N value of the divider to give
us 25kHz from the divided down RF of the LO frequency. Take (118.3MHz +
10.7MHz)/25kHz = N or 5160. Now the dividers are set up to request this LO
frequency, however the VCO has not been tuned there yet. If there is any error
between the “C” output and the “N” divider output, which there should be after
switching the N divider, an internal comparator looks at the two 25kHz signals
together then provides error correction pulses to tune the VCO to correct the
difference.
For example the VCO frequency is too low, which results in 24.999kHz output
at the N divider rather than 25kHz at the C divider. The PLL comparator output
will then provide some high-going pulses to the PLL filter (U5:A and
surrounding parts) to bring the tuning voltage up so the 25kHz divider outputs
begin to come closer. Once the two frequencies match, small error pulses “tap”
the VCO to keep it “phase locked” to the divided reference clock and make up
for any environmental changes such as temperature and vibration.
The PLL filter removes the comparator error correcting pulses of 25kHz by low-
pass filtering them. These tuning filters are also called integrators since they
have no DC feedback. What results is a steady tuning voltage that allows the
VCO to change smoothly from one channel to the next without 25kHz signals