manualshive.com logo in svg

Radio Shack TRS-80 Model 100, Service Manual, Page: 62 / 127

Share
Download
Radio Shack TRS-80 Model 100 Service Manual Download Page 62

Summary of Contents for TRS-80 Model 100

Page 1: ...MODEL I OO PORTABLE COMPUTER Catalog Numbers 26 3801 3802 CUSTOM MANUFACTURED FOR RADIO SHACK H A DIVISION OF TANDY CORPORATION Radio hack ServiceMmmiD 26 3801 3802...

Page 2: ...SCRIPTION KEYBOARD CASSETTE INTERFACE CIRCUIT PRINTER INTERFACE CIRCUIT BARCODE READER INTERFACE CIRCUIT BUZZER CONTROL CIRCUIT SYSTEM BUS LCD INTERFACE CIRCUIT CLOCK CONTROL CIRCUIT SERIAL INTERFACE...

Page 3: ...on OF OPTIONAL RAMs AND ROM appendix b character code table APPENDIX C LSI DESCRIPTION MSM80C85ARS CPU MSM81C55RS PIO C 1 IM6402 UART C11 MPD1990AC TIMER 015 MC14412 MODEM C 19 TC5518BF 25 RAM C 24 LH...

Page 4: ...ondition of uPD1990AC Time Read Condition of iPD1990AC Data Output Condition of iPD1990AC Control Register Load Condition of IM6402 Status Read Condition of IM6402 Data Transmission Condition of IM640...

Page 5: ...C 21 O 1 C 18 C 19 A PD1990AC Command Input Timing Diagram iPDI 990AC Data Input Output Timing Diagram C 22 C 23 C 26 O ZU C 26 C 26 C 27 w Zo TPRR1 RRF 9R Pin 1 avnut C 28 r ok C 29 U Z J C 29 u Zu C...

Page 6: ...SECTION I INTRODUCTION...

Page 7: ...FRONT VIEW 1 1...

Page 8: ......

Page 9: ...del 100 Section VI This section provides a part list and an exploded view of the TRS 80 Model 100 Section VII This section provides schematics P C Board diagrams and silk screen views of P C Boards of...

Page 10: ...icture control keys Function keys Special symbol keys Mode keys Other special use keys b LCD display Display panel 27 10 7 8 8 5 6 240 x 64 Full dot matrix c d e 1 32 Duty 1 6 66 Bias Dot pitch 0 8 x...

Page 11: ...e 75 110 300 600 1200 2400 4800 9600 19200 BPS Maximum Transmission Distance 5 meters Driver maximum voltage output 5 volts Driver minimum voltage output 3 5 volts Receiver maximum voltage input 18 vo...

Page 12: ...to turn the power ON To conserve the batteries the Model 100 automatically turns the power off if you do not use it for 10 minutes When an automatic power off occurs the switch will still be in the O...

Page 13: ...be backed up when this switch is set to the OFF position ON OFF e RESET Switch If the Model 100 lock up ie the display will freeze and all keys seem to be inoperative press this button to return to th...

Page 14: ...SECTION II DISASSEMBLY REASSEMBLY...

Page 15: ...snaps Also do not apply too much force when pulling open the LCD and keyboard connectors are attached 3 Remove the LCD and key board connectors from the main P C B 4 Remove the buzzer connector from...

Page 16: ...B supports with the holes in the P C B and attach them so that they fit to the P C B edge 2 Align the K B supports and K B P C B holes with the upper case screws 3 Attach the K B supports and K B P C...

Page 17: ...SECTION III PREVENTIVE MAINTENANCE...

Page 18: ...lint free cloth 3 For tough stains clean the body or LCD using benzol Do not use any other solvents except for benzol MODEM TRANSMITTING LEVEL ADJUSTMENT 1 Set the DIR ACP switch to DIR position 2 Co...

Page 19: ...SECTION IV THEORY OF OPERATION...

Page 20: ...T This is the Universal Asyncronous Receiver Transmitter which controls the serial interface RS 232C or MODEM The Input Output for a cassette recorder and the Input of the BCR are controlled by CPU di...

Page 21: ...ormance with higher system speed The 80C85 uses a multiplexed data bus The CPU bus is divided into two sections the 8 bit address bus and the other 8 bit address and data bus For the Model 100 the dat...

Page 22: ...bottom case of the Model 100 Various types of application programs may be stored in the optional ROM ADDRESS DECODING AND BANK SELECTION 1 Address decoding for RAM chip selection Although four 8KB RAM...

Page 23: ...LSB Address decoding for RAM chip 16 F800H to FFFFH Fig 4 3 Address Decoding for RAM Chip 4 4 u CO...

Page 24: ...wn in Fig 4 4 ADO is latched at Ml4 TC40H175 quad D type F F by WR signal and Y6 Then STROM signal is generated refer I O port description The chip select signal of each ROM is generated by the IO M s...

Page 25: ...MEMORY MAP 8000 H E000H FFFFH 77 y Cl STANDARD Addressing of additional RAMs start from higher address Fig 4 5 Memory Map 4 6...

Page 26: ...ct signal of various circuits made by user 80H 8FH YO L Device select signal for optional I O controller unit 90H 9FH Y1 L Device select signal for optional answering telephone unit AOH AFH Y2 L Bit 0...

Page 27: ...ower byte B5H or BDH Timer register upper byte B6H B7H B8H and B9H Not used Table 4 2 I O Address of Each Port KEYBOARD Key strobe signals are emitted from PBO and PAO PA7 of 81C55 and the return sign...

Page 28: ...the data passes through an integrator consisting of R51 and C64 and after voltage division out to a recorder AUX inputs Figure 4 8 shows the modulation circuit of the Cassette Interface CMT Connector...

Page 29: ...the condition is NOT BUSY PC2 L level the 8 bit data PAO PA7 from 81C55 is sent to the printer By writing in data 1 into bit 1 of the output port 40H175 M14 indicated by I O address EOH EFH T8 is swi...

Page 30: ...LINE Fig 4 12 Bar Code Reader Interface Circuit BUZZER CONTROL CIRCUIT There are two ways to activate the buzzer One is to sound buzzer with the specified frequency by emitting a signal from PB5 of 81...

Page 31: ...Signal Input or output Pin No Signal Input or output 1 VDD 40 VDD 2 GND 39 GND 3 ADO In output 38 ADI In output 4 AD2 In output 37 AD3 1 n output 5 AD4 In output 36 AD5 1 n output 6 AD6 In output 35...

Page 32: ...eft High level output voltage VOH 2 4V min IOH 400 mA 4 95V min IOH 1 iA Low level output voltage VOL 0 45V max IOL 2 mA 0 05V max IOL 1 fiA High level output current IOH 400 nA min VOH 2 4V 0 8 mA mi...

Page 33: ...he LCD driver SI L or read out SI H A8 Register select signal in the LCD driver ADO AD7 data are display data when A8 H and are command or status data when A8 L E NAND output signal of RD signal and W...

Page 34: ...PA4 terminals and DATA OUT terminal is connected to the 81C55 PCO terminal The STB signal is provided from bit 2 of the output port made by M14 40H175 The TP output signal is connected to the RST7 5 i...

Page 35: ...e 010 pattern of CO C2 and the strobe signal Fig 4 17 Time Set Condition of L PD1990AC b Time Read Sequence The CPU sets mPD1990AC to the time read mode with the 110 pattern of CO C2 and the strobe si...

Page 36: ...terface circuit is divided into three parts serial control RS 232C and Modem The serial control circuit controls the changes and transmission reception of data parallel data and serial between the CPU...

Page 37: ......

Page 38: ...55 Fig 4 21 Status Read Condition of IM6402 When the TBRE signal becomes H data transmission is possible If the transmission data is written into the transmitter buffer register TBR1 TBR8 the data is...

Page 39: ...status input port M23 If there is no error when the serial data is received the reception data from the receive buffer register selected by Y4 can be read as 8 bit parallel data The IM6402 serial tran...

Page 40: ...forms IM6402 is one channel only the circuit shown in Fig 4 24 is multiplexed to RS 232C and the MODEM The RS 232C signal PB3 terminal of 81C55 determines whether the serial port is to be used as RS...

Page 41: ...32C line are subjected to waveform shaping and inverted by M35 and diode 1S1535 and then converted to 5V or_GND level signals The signals are then demultiplexed by 40H157 M33 and converted to CTS DRS...

Page 42: ...047 50V rigJ ANS ri2uj Jmm Jl CARRIER FREQUENCY 2125 Hz ORIGIN MODE Fig 4 26 MODEM LSI and Peripheral Circuit 5 Transmission Filter Circuit USA version only The transmit carrier signal output from the...

Page 43: ...g changed to a square wave is input at the RX CAR terminal of MCI4412 Intermediate frequencies of the 3 stage active filter are shown below The switching of intermediate frequency for the Originate an...

Page 44: ...former is connected to the telephone line via the connector TXMD RXMD The ACP DIR switch is used for selection of the acoustic coupler or the direct method of connection to the telephone line When the...

Page 45: ...h its appearance is much like a liquid From an electrical and optical stand point it possesses the properties of a crystal Items which use this substance are called liquid crystal display elements The...

Page 46: ...nd lower plates are placed at right angles to each other to use the optical twisting of light 2 As shown in Fig 4 31 a if voltage is not applied the liquid crystal molecules between the upper and lowe...

Page 47: ...e field of vision is 30 in the range that contrasts K 1 4 or more brightness of non illuminated segment brightness of illuminated segment This range can be set at will from 0 to 90 by adjusting the LC...

Page 48: ...3 shows the internal logic composition Selector Fig 4 34 HD44103 Internal Logic Diagram The timing signals are M FRM CLK 0i 02 and CL The M signal inverts the LCD drive waveform one image at a time to...

Page 49: ...lower the M5 and M10 segment output Y41 Y50 becomes NO CONNECTION The power supplied to these IC s in addition to VDD 5V and VEE 5V also includes VI V6 VDD and VEE are the power supplies which operate...

Page 50: ...ther dots on the same signal electrode The maximum voltage applied to the Common electrode and Segment electrode is the potential dif ference between VI and V2 In addition a is the bias coefficient wh...

Page 51: ...ction T21 and T22 are switched ON once again and oscillation such as that shown in Fig 4 38 occurs In this way AC voltage corresponding to the number of windings is generated at the secondary side of...

Page 52: ...minutes or more P C S is output from PB4 of 81C55 When the power switch is switched OFF T18 is switched OFF the M28 RESET terminal becomes H and oscillation is resumed by switching the power switch O...

Page 53: ...switched OFF about 20 sec after VDD is activated with the result that the RESET signal changes from L to H In the same way RAM RST signal is generated by T9 and changes from H to L R141 provides hyste...

Page 54: ...SECTION V TROUBLESHOOTING...

Page 55: ...hooting Flowchart and refer to the section indicated by the number Each section then identifies the components associated with the circuit in question and provides remedial instructions After completi...

Page 56: ...TROUBLESHOOTING GUIDE...

Page 57: ...A...

Page 58: ...1 Doesn t work at all...

Page 59: ...al Refer to 6 Reset doesn t function Check the LCD waveform If abnormal check the LCD power supply operation amplifier Check the interface circuitry Check all IC s connected to the bus line M17 and M2...

Page 60: ...from the TP terminal pin 10 of Ml8 and M25at 4 msec intervals Check M15 M13 M16 and pull up resistor MR4 Check connector connections Check if LCD connector is correctly connected Check if buzzer conn...

Page 61: ...5 Clock doesn t function 6 Reset doesn t function...

Page 62: ...7 Memory protection doesn t function...

Page 63: ...9 Cassette interface doesn t function 10 B C R interface doesn t function...

Page 64: ...ansmission Then check if the CTS signal of pin 5 is low level If not output check M22 M24 M35 C75 C76 C77 C71 C72 and C73 Check receive side Check if a digital signal is input to M22 pin 20 RRI termin...

Page 65: ...12 Modem interface doesn t function 13 All functions check ok 5 11...

Page 66: ...unctions work 4 Reset function test memory protection test a Warm start Turn the Computer OFF and then ON or with the POWER switch ON press RESET on the rear Check that all User files are displayed b...

Page 67: ...SECTION VI EXPLODED VIEW AND PARTS LIST...

Page 68: ...6...

Page 69: ...P 21 EXPLODED VIEW CASE ASSEMBLY Fig 6 2 Bottom View...

Page 70: ...CITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CAPACITOR CERAMIC 82PF 50V H 10 CERAMIC 0 04 7aiF 25V 10 CERAMIC...

Page 71: ...471ACX C84 CAPACITOR ELEC 470MF 6 3V 30 10 ACC 477RBAP CEAB471ACX C85 CAPACITOR ELEC 33mF 10V 20 ACC 336MCAP CEAC330ADN C86 CAPACITOR ELEC lOO F 6 3V 75 10 ACC 107XBAP CEAB101ALN C87 CAPACITOR CERAMIC...

Page 72: ...SILICON ZENER NEC RD4 3 EL3 DIODE SILICON 1S2076 ADX 1860 DIODE SILICON 1S2076 DIODE SILICON ERA81 004 DIODE SILICON ZENER NEC RD5 1 ELI DIODE SILICON 1S2076 I DIODE SILICON 1S2076 SURGE ABSORBER ERZ...

Page 73: ...GATE TC40H032P AMX 5812 QQ040032AT M2 5 I C C MOS PI O MSM81C55RS AMX 5807 QQ008155A5 M26 I C HI SPEED C MOS NOR GATE TC40H002P AMX 5811 QQ040002AT M27 I C C MOS NAND GATE MN4011B OR AMX 5802 QQ004011...

Page 74: ...l 4W l CARBON 10K OHM 1 4W 5 METAL FILM 1 30K OHM l 4W l METAL FILM 3 3K OHM l 4W l METAL FILM 28OK OHM 1 4W l METAL FILM 422K OHM 1 4W l CARBON 2 2K OHM l 4W 5 CARBON 22 OHM l 4W 5 CARBON 10K OHM 1...

Page 75: ...BON 33K OHM 1 4W 5 RD25PJ333X R85 RES CARBON 10K OHM l 4W 5 RD25PJ103X R86 RES CARBON 33K OHM l 4W 5 RD25PJ333X R8 7 R88 RES CARBON 6 2K OHM 1 4W 5 r RD25PJ622X R89 RES CARBON 6 2K OHM 1 4W 5 RD25PJ62...

Page 76: ...J683X R136 RES CARBON 68K OHM l 4W 5 RD25PJ683X R137 R138 RES CARBON 10OK OHM l 4W 5 RD25PJ104X R13 9 RES CARBON 100K OHM l 4W 5 RD25PJ104X R140 RES CARBON 10K OHM l 4W 5 RD25PJ103X R141 RES CARBON 1M...

Page 77: ...T19 XSISTOR 2SA1115 NO RANK PC300MW FT200MH T2 0 XSISTOR 2SC2603 NO RANK PC300MW FT200MH AA 2 SC 2 6 0 3 T21 XSISTOR 2SC1384 S RANK PC750MW FT200MHZ T22 XSISTOR 2SC2603 E RANK PC300MW FT200MHZ T23 XSI...

Page 78: ...Ml 7X3 S BLACK AHD 2593 BSP21703NB S 7 SCREW PAN HEAD SEMS MACHINE M3X8 S ZNCR AHD 2594 BSPC3008NZ S 8 NUT M3 Z ZNCR THIN TYPE AHD 728 4 BNHCL30NSZ LCD P C B ASSEMBLY Description RS Part No Mfr s Part...

Page 79: ...J104 LR7 LR8 LR9 r LR10 RESISTOR CHIP 100K OHM l 8W 5 RJ8AMJ104 LRll RESISTOR CHIP 18 OHM 1 8W 5 RJ8AMJ180 LR12 RESISTOR CHIP 150 OHM 1 8W 5 RJ8AMJ151 LRl3 LRl 4 LRl 5 r f LR16 RESISTOR CHIP 150 OHM l...

Page 80: ...T P 217 KEYTOP ENTER P 218 KEYTOP SPACE AK 5205 VK121SB003 AK 5206 VK122SB004 AK 5207 VK122SB005 AK 52 08 VK122SB006 AK 5209 VK122SB007 AK 5210 VK122SB008 AK 5211 VK122SB009 AK 5212 VK122 SB010 AK 521...

Page 81: ...E AHC 2181 KLXl 01 P 4 LABEL FCC 26 3801 USA VERSION ONLY KL000304XX 26 3802 USA VERSION ONLY KL000305XX P 5 PLATE SERIAL NUMBER 26 3801 MVSX1 1 26 3802 MVSXl 2 P 1 SUPPORT KEYBOARD FRONT AHC 2182 MU8...

Page 82: ...4 SECTION VU DIAGRAMS...

Page 83: ...Main P C B Schematic Diagram...

Page 84: ...LCD P C B Schematic Diagram...

Page 85: ...Ittaxra ift rjcrflW irarrai Syrwi m m01 SSU HSyZXB IJJ UiAXia gajLJ ra jTt i Cm mg aaBjggg P C B VIEWS MAIN P C B TOP VIEW Fig 7 3 Main P C B Component Side 7 3...

Page 86: ...MAIN P C B BOTTOM VIEW Fig 7 4 Main P C B Circuit Side 7 4...

Page 87: ...LCD P C B VIEWS...

Page 88: ...APPENDIX A INSTALLATION OF OPTIONAL RAMs AND ROM...

Page 89: ......

Page 90: ...hat all the pins of the RAM are correctly aligned against the socket pins 2 Installation of optional ROM Using the coin remove the ROM Cover on the Bottom Case You will find an 1C socket with a plasti...

Page 91: ...APPENDIX B CHARACTER CODE TABLE...

Page 92: ...T 66 42 01000010 B B 21 15 00010101 CTRL U 67 43 01000011 c c 22 16 00010110 CTRL V 68 44 01000100 D D 23 17 00010111 CTRL W 69 45 01000101 E E 24 18 00011000 CTRL X 70 46 01000110 F F 25 19 00011001...

Page 93: ...owercase letters a z be sure CAM LACK is not pressed down Decimal Hex Binary Printed Character Keyboard Character 144 90 10010000 ft fflffiy 145 91 10010001 a 380 u 146 92 10010010 l 080 147 93 100100...

Page 94: ...100 Y BSE Y 221 DD 11011101 U BSE 222 DE 11011110 E BSE V 223 DF 11011111 A BSE X 224 ED 11100000 38SCZ 225 El 11100001 upper left ggff 226 E2 11100010 upper right 8E 227 E3 11100011 lower left 228 E4...

Page 95: ...4 APPENDIX C LSI DESCRIPTION...

Page 96: ...Central Processing Unit CPU It s instruction set is a full compatible with the 8080A microprocessor InIK RST65 TRAP Fig C 1 80C85 Functional Block Diagram Xi T 751 Vcc x2 F 39l HOLD reset xrr T J8 HL...

Page 97: ...ddress information The falling edge of ALE can also be used to strobe the status information ALE is never 3 stated Machine cycle status IO M S So Status 0 0 1 Memory write 0 1 0 Memory read 1 0 1 I O...

Page 98: ...l be inhibited from incrementing and an INTA will be issued During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine The INTR is enabled and disabled by...

Page 99: ...al clock generator Xi can also be an external clock input from a logic gate The input frequency is divided by 2 to give the processor s internal operating frequency Clock Output for use as a system cl...

Page 100: ...bit Address Data Bus During the first T state clock cycle of a machine cycle the low order address is sent out on the Address Data bus These lower 8 bits may be latched externally by the Address Latch...

Page 101: ...the end of the RST7 5 routine The TRAP interrupt is useful for catastrophic events such as power failure or bus error The TRAP input is recognized just as any other interrupt but has the highest prior...

Page 102: ...mand lines A machine cycle normally consists of three T states with the exception of OPCODE FETCH which normally has either four or six T states unless WAIT or HOLD states are forced by the receipt of...

Page 103: ...80C85 Basic System Timing Ambient Temperature Under Bias 40 C to 85 C Storage Temperature 55 C to 150 C Voltage on Any Pin with Respect to Ground 0 5 C to 7V Power Dissipation 1 0 Watt_ Table C 4 80C...

Page 104: ...LDR RD _ U y Write Operation CLK A8 A15 T i_I T 2 t lck As Ais ADDRESS T AD0 AD7 ADDRESS X I tLL tLA K ALE r l JjJWDLi Twait T3 DATA OUT HI1 twn j t LC f fn rx _zz_lcc_ _ jbrf tAC tARY T RY i tLRY Re...

Page 105: ...t INS M t INH HOLD m tHDS tHDH HLDA tHACK Fig C 8 80C85 Interi C...

Page 106: ...PA AD5 Q_7 24 PA j ADs 78 23 PA AD7 Q9 22 PA i gndUo I PAo IO M ADo 7 CE ALE RD WR RESET 256x8 STATIC RAM TIMER TIMER CLK TIMER OUT PORT A DO PAo 7 PORT B PORT C l 1 PBo 7 c PC 0 5 Vcc 5 V GND 0 V Fi...

Page 107: ...f the Chip Enable and IO M into the chip at the falling edge of ALE Selects memory if low and I O and command status registers if high These 8 pins are general purpose I O pins The in out direction is...

Page 108: ...C 13...

Page 109: ...a Strobed Input Mode b Strobed Output Mode Fig C 11 81C55 Strobed I O Timing a Basic Input Mode RD INPUT tRP t PR V_ r _ _ DATA BUS _ IX b Basic Output Mode Fig C 12 81C55 Basic I O Timing C 14...

Page 110: ...and one half when transmitting 5 bit code The IM6402 can be used in a wide range of applications including modems printers peripherals and remote data aquisition systems CMOS LSI technology permits o...

Page 111: ...pply I NC No Connection GND Ground RRD A high level on RECEIVER REGISTER DISABLE forces the receiver holding outputs RBR1 RBR8 to a high impedance state RBR8 The contents of the RECEIVER BUFFER REGIST...

Page 112: ...ransferred to the receiver buffer register RRI Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register MR A high level on MASTER RESET clears PE FE OE and DR to a low level and se...

Page 113: ...TBR1 CRL A high level on CONTROL REGISTER LOAD loads the control register PI A high level on PARITY INHIBIT inhibits parity generation Parity check ing and forces PE output low SBS A high level on STO...

Page 114: ...timing pulse outputs Selection of 64 Hz 256 Hz or 2048 Hz is possible By using the CS chip selection terminal multi chip applications are possible b Function specifications Reference frequency Xtal os...

Page 115: ...t Prohibits CLS STB Output control input Makes the DATA OUT high impedance by inputting low level Data output of 40 bit shift register Time pulse output Oscillation inverter input OSC IN Oscillation i...

Page 116: ...d Block Diagram OUT ENBL CLK DATA...

Page 117: ...i MIN Fig C 18 iPD1990AC Command Input Timing Diagram Commands designated by C0 Ci and C2 will be written into the latch when the STB terminal becomes high level and will be held until a different com...

Page 118: ...f Data Input Output Timing Diagram appears at output Input Timing Output Timing Fig C 19 jPD1990AC Data Input Output Timing Diagram C 23...

Page 119: ...frequencies for both transmitting and receiving data When the Type input 1 the U S standard is selected and when the Type input 0 the C C l T T standard is selected Tx Data Transmit Data is the binar...

Page 120: ...or This input must have either CMOS or TTL compatible logic level input see TTL pull up disable at a duty cycle of 50 4 that is a square wave resulting from a signal limiter The demodulator has been o...

Page 121: ...TTLD...

Page 122: ...To Telephone Network Fig C 23 MCI4412 Input Output Signals...

Page 123: ...h are used for device selection and can be used in order to achieve the minimum standby current mode easily for battery back up TOP VIEW VDD AS Ag R W CE_i A10 lA s l Oy i oe 1 05 i o4 Fig C 24 TC5518...

Page 124: ...Addresses CE2 CEi D0UT Fig C 25 TC5518BF 25 Block Diagram Fig C 26 TC5518BF 25 Read Timing Diagram...

Page 125: ...Write Cycle 1 Write Cycle 2 UNKNOWN Fig C 27 TC5518BF 25 Write Timing Diagram C 30...

Page 126: ...L 27 CS At cr 261 As Ae 25 l Ao As CE 24 A12 a4 CE 23l CE AaE 22 A 3 A 1 8 TTI oe a HE 20l Au Ao cc HI Dt do qr 1F1 Ds D QT m db Da QT he D gnpHT jE d3 Fig C 28 LH 535618 Pin Layout Pin Name Descripti...

Page 127: ...Fig C 29 LH 535618 Block Diagram Fig C 30 LH 535618 Timing Diagram...

Reviews:

No comments