Radio Shack 26-3801 Service Manual Download

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Summary of Contents for 26-3801

Page 1: ...Radio haeti Service MODEL 100 MICROCOMPUTER 26 3801 PRELIMINARY PRODUCT INFORMATION 0220 TECHNICAL SUPPORT SERVICES...

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Page 3: ...MODEL 100 SERVICE MANUAL 0220 TECHNICAL SUPPORT DOCUMENTATION LIBRARY...

Page 4: ...ap 5 I O Map and I O Port Description 6 Keyboard 7 cassette Interface Circuit 8 Printer Interface Circiut 9 Bar Code Reader Interface Circuit 10 Buzzwe Control Circuit 11 System Bus 12 LCD Interface C...

Page 5: ...3 VI TROUBLE SHOOTING 1 Trouble Shooting Guide 2 Chevking Procedure 3 Check List VII PRINED WIRING BOARD MAIN P W BOARD LCD P W BOARD...

Page 6: ...CONFIDENTIAL SECTION 1 INTRODUCTION...

Page 7: ...itch 0 8x0 8mm Dot Size 0 73 x 0 73 mm Effective Display Area 191 2 x 50 4 mm b c d Case Dimensions 300 Material ABS Operation Batteries Batteries W x 46 5 L x 215 H mm Operation time e Four alkali ma...

Page 8: ...RS 232C Conforms to EIA standards Signal TXR Transmit Data RXR Receive Data RTSR Request To Send CTSR Clear To Send DSRR Data Set Ready DTRR Data Terminal Ready Programmable Items Data Length 6 7 or...

Page 9: ...Rate 1 500 BPS MARK 2 400 Hz SPACE 1 200 Hz d Printer Interface Conforms to Centronics Interface standards Handshake Signal STROBE BUSY SELECT 3 Special functions a Automatic power OFF When there is n...

Page 10: ...er Switch This is the PPC system power switch OKJ IflD OFF ON ED OFF Power OFF Power ON Fig 1 b ANS CALL selector This switch is used to select the MODEM ANSWER mode or CALL mode ams j HDi oRiq AWS ED...

Page 11: ...he RAM will not be backed up when this switch is set to OFF OM H Off ON H OFF MfEMORY BACk UP OM MEMORY BACk UP OFF Fig 4 Reset switch push switch This switch initializes resets the system A cold star...

Page 12: ...1 1 Z 3 1 1 1 f 1 Y Q_ A ul a _j 2 2 C Ifl olcgj t JJU V E J 1 W H tlin Is K i j 111 m l io 3E idRF _J ai h 2 LU U OL s OIE i_ 3 O H 00 u CO s 1 a o to CS J cr j o vO 1 U r Kt Q LU v X J M 4 ro a 00 1...

Page 13: ...I I Q o a UJ V V 2T GC O UJ a U7 CD A td E E tu H 00 X UJ CO t _J UI V VO c j CO 3 Cd c X a JC 35 M a CO 3 CD U U U m u CD CP E i j O X ID V 1 H V S a 3 co XJ 0 X 5 1 Ci2 ro to Nl u m CM U et cc CM a...

Page 14: ...CO i Ul r J v n 0 I f 5 r 1 1 I im i i CL A j LU Q O _J w O UJ V t UJ CO r H 3 z V j Si 1 Q3 CO o i u Q_ q J jo co Q LU in X U 1 Ol I M U J 0 cr 1 I cO o J c i u_ T co CNf a o u_ T V7X o O J u_ o en...

Page 15: ...o o M ro CO UJ V Of i CD I Cd s UJ o Q_ CO r CT i Id CXI S LO o J Cd co CO J Ui CO Ui 2 i o r E c rQ JZ Cd GO U JD 3 M 1 u CD E C Cd u J u UJ u m u LO Cd Cd v_ M O S J 3 r Cd O CD i O X Q X CO Cd to...

Page 16: ...L 4 ro I l_J QL on M io i h or UJ o T _jjro a IE O u_ Q CO O A V 2 o CD O X M UJ u CL en 6 a W o 3 e 00 a M m bd Cd W CO H o zz a c o 2 Q 1 i Cil s M s _J J a co J h M a co d cs co s M S 2 o a M c co...

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Page 23: ...4 LCD CHARACTER FONT T ITFS bVd3 KS53 j C __ _j_i_ 88 89 W HJEE mnhi fj i lj j_l 9 33k i 1 _u_ M yj I t t i i i i 95...

Page 24: ...R ft 40 I M M H IB 42 I y i l 1 i j i i i i 43 EJK EST t i I M l t 33 1 mi r i r ZlJTjJI C J rniTr M rU 46 147 zc 48 4 9 J M r_ _J_ _ J 150 Tffj FlS Tlffl rJU1 Effiib EhtfcE 152 IT3 Rm 4 B V 54 FFU 3...

Page 25: ...193 ITM IH Ji p f u 7 rlv 195 S2I P nTi i i a 97 00 20 _J _I i estb Hffl ess mm FUSF M M I I n l W mb F ti riTTi n HT i n hiHl i HiHrrn EH rr 2 o 3 204 5 pmJJ X nXP F 208 209 210 211 2 12 215 FF ft T...

Page 26: ...2Z 224 Wt p p 225 226 221 2 8 29 230 j J j 1 231 232 233 _ UA 235 3 6 23 238 239 11 0 241 24 1 24 24 4 ffl 24 6 247 249 250 252 253 254 a I j i 5...

Page 27: ...2 3 en O Q O CVJ V 2 o o S CO OS o at j a ca H a o w a H UJ LU q o CO in I ca Q 1 T o 1 i 1 1 X 1 s UJ 00 en N ro i ID o Q T U3 en o...

Page 28: ...Z SECTION II DISASSEMBLY REASSEMBLY...

Page 29: ...so don t apply too much force when pulling open because the LCD and K B connectors are attached 3 Remove the LCD and K B connectors from the main PWB C4 Remove the buzzer connector from the LCD PWB 2...

Page 30: ...2 K B supports with the holes in the PWB and attach them so that they fit to the PWB edge 2 Align the K B supports and K B PWB holes with the upper case screws 3 Attach the K B supports and K B PWB t...

Page 31: ...2 SECTION III MAIN P W BOARD...

Page 32: ...1 LSIs 1 MSM80C85ARS CPU 1 chip 8 bit C MOS Process Microprocessors The MSM80C85ARS 80C85 is a complete 8 bit parallel Central Processing Unit CPU Its instruction set is 100 software compatible with...

Page 33: ...a 80C85 FUNCTIONAL PIN DESCRIPTION The following describes the function of each pin Symbol A Ais Output 3 state Function Address Bus The most significant 8 bits of the memory address or the 8 bits of...

Page 34: ...low level on RD indicates the selected memory or I O device is to be read and that the Data Bus is available for the data transfer 3 stated during Hold and Halt modes and during RESET WR Output 3 stat...

Page 35: ...e interrupt It is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states If it is active the Program Counter PC will be inhibited from incrementing and...

Page 36: ...y The cpu is held in the reset condition as long as RESET IN is applied RESET OUT Output Indicates cpu is being reset Can be used as a system reset The signal is synchronized to the processor clock an...

Page 37: ...bits x 3 pointer HL SP Stack Pointer 1 6 bit address Flags or F Flag Register 5 flags 8 bit space The 80C85 uses a multiplexed Data Bus The address is split between the higher 8 bit Address Bus and th...

Page 38: ...the 80C85 The RST 7 5 internal flip flop will be set by a pulse on the RST 7 5 pin even when the RST 7 5 interrupt is masked out The status of the three RST interrupt masks can only be affected by th...

Page 39: ...er 8 bits of address on the Data Bus Fig 4 shows an instruction fetch memory read and I O write cycle as would occur during processing of the OUT instruction Note that during the I O write and read cy...

Page 40: ...X X X X X X T t 0 X TS I TS 1 0 X TS I T I 1 j X j TS 1 1 TRES6T 1 X TS TS TS TS f o TMALT j TS i TS TS TS i o THOLD i X TS i TS j TS TS 1 o 3 Table 3 80C85 MACHINE STATE CHART T T T T III IlT lF CLK...

Page 41: ...ut Low Level RESET 0 3 0 8 V V HB Input High Level RESET 2 2 vcc 0 3j v 7 Table 5 D C CHARACTERISTICS w 1 2IT 45 MIN la 1 2 T 60 MIN t L 1 2 T 20 MIN t CK 1 2 T 60 MIN t LC 1 2 T 30 MIN l AD 5 2 N T 2...

Page 42: ...Edge of CLK INTR Hold Time INTR RST and TRAP Setup Time to Falling Edge of CLK Address Hold Time after ALE Trailing Edge of ALE to Leading Edge of Control ALE Low during CLK High ALE to Valid Data dur...

Page 43: ...X r i i i u_j V AOOBKS Z y fATAIW 10 I fr CA fc _ Write Operation a u_y v iCK AO O 11 P HH OW j BB u r e wot f rzn Read operation with Walt Cyclt Typical tame READY timing appllea to WRITE operation...

Page 44: ...Hold Operation 4 r i _y i r i AODfUtt CONTROLS I hack H t HABf Fig 7 Hold Timing v h M 3t s IO S IS ALSO FLOATING DURING THIS TIME Fig 8 80C85 Interrupt and Hold Timing...

Page 45: ...unt pulse for the CPU system depending on the timer mode The 81C55 RAM is not used in Model 100 A timer counter is used as the clock generator necessary for communication and to generate the melody K...

Page 46: ...the chip or read from the chip depending on the WR or RD input signal CE Input Chip Enable CE is ACTIVE LOW RD Input Read control Input low on this line with the Chip Enable active enables and ADo 7 b...

Page 47: ...put port output port or as control signals for PA and PB Programming is done through the command register When PC _s are used as control signals they will provide the following PC A INTR Port A Interr...

Page 48: ...ROF Data Bus Float After READ 100 tCL READ WRITE Control to Latch Enable 20 tec HEAD WRITE Control Width 250 DW Data In to WRITE Set Up Time 150 two Data In Hold Time After WRITE tRV Recovery Time Be...

Page 49: ...UadCycl CT X Z V re X ex fcrzXZ A f Jf v r b WrftaCyel CtMISN PO fl wft z X 3 z IA X j j f DATA VALID T v Fig 10 81C55 Read Write Timing Diagram...

Page 50: ...u a Strobed Input Mod rrxou re INTUT DATA FROM nMT A Hu VL N i y x _f z b Strobad Output Mod IF ETRfiU OR OUTPUT DATA TOKWT jL J z X Fig 11 Strobed I O Timing...

Page 51: ...OATA BUS TIMING IS SHOWN IN FIQUMI 7 Fig 12 Basic I O Timing X i f X LOAD COUNT FROM I 1 I TwrrBOT ISOUAftf WAV I NOTE 1 THt TIMf OUTFUT IS 1 1 MOOIC IF IN AN AUTOMATIC ftCLOAO OOOJ IM MOO SIT II V7 F...

Page 52: ...a aquisition systems CMOS LSI technology permits operation clock frequencies up to 2 0 MHz 125K Baud an improvement of 10 to 1 over previous PMOS UART designs Power requirements by comparison are redu...

Page 53: ...4 V IOH 0 2mA VOL Logical 0 Ouipul Voltage 0 45 V IOL 2 0mA 10 Output Leakage 10 0 10 0 fJA OV VO vcc ICC Supply Current 1 0 800 MA V N GNO or VCC VCC 5 25V ClN Input Capacitance 7 0 8 0 PF Output Oo...

Page 54: ...ignificant bits will be a logic low The output character is right justified to the least significant bit RBR1 A logic high on OError indicates overruns An overrun occurs when DReady has not been clear...

Page 55: ...32 bit or 3 125 giving a receiver margin of 46 875 The receiver begins searching for the next start bit at the center of the first stop bit _rLn_n Tj i_nji_njxn r Fig 17 _ i_ ct n r it I 11 Of f H d...

Page 56: ...transferred to the received buffer register A high level on STATUS FLAGS DISABLE lorces the outputs PE FE OE DR TBRE to a high impedance state The RECEIVER REGISTER CLOCK is 1 6X the receiver data rat...

Page 57: ...on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including stop bits Character data start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT Character...

Page 58: ...CLS1 low CLS2 high 7 bits CLS1 high CLS2 high 8 bits See Pin 37 CLS2 When PI is low a high level on EVEN PARITY ENABLE generates and checks even parity A low level selects odd parity The TRANSMITTER R...

Page 59: ...nsition occurs simultaneously with or latter from the R W low tran sition in a Write Cycle 1 the output bulfers remain in a high impedance state in this period 5 If the CE i or CE2 high transition occ...

Page 60: ...aximum Rating SYMBOL vaa_ Vw PARAMETER Power Supply Voltage Input High Voltage input Low Voltage iaa_ Data Retention Voltage 4 5 2 2 0 3 Plastic FP 0 45W 5 0 5 5 UNIT V Vpn 0 3 I v_ 5 5 Table 17 Recom...

Page 61: ...h 150 ns AW Address Set up Time i ns lyVB Write Recover Time i _ ns OOW Outoui High Z Irom R W 60 ns OEW Output Active irom R W io ns IDS Oata Set uo Time 1 90 ns tnw Oau Hold Time 1 1 ns Table 20 A C...

Page 62: ...Memory Model 100 has a RAM Pack consisting of four 2 KB RAMs each 2048 X 8 bit mounted on the ceramicmother board for a total of 8 KB 8192 X 8 bit the standard equipment RAM pack is the M9 with the M8...

Page 63: ...9 t 2 a Q o o a 2 r 5 ffS5Ss sss o Is 1 7 77 i r M I II II I M I 5T I I i 1 1 1 1 1 M II II II I II 5 51 Jz I II I II I I I I I zk mmmnJn j i 133 2 33 Jt U rl2l i i L_ i iz_ a M 5a...

Page 64: ...el 100 Various type of application program can be entered in the optional ROM ADDRESS DECOING AND BANK SELECTION 1 Address decoding for RAM chip selection Although four 8 KB RAM packs are attached to...

Page 65: ...00 for RAM chip H 87FF H _I F W W o o o o o o o o o o o o l ffi a Y b r A Y 5 ai C B A 14 1 O i i i4 ft 1 73 1 i 777 1 7 1 5 ff B Qt C 8 A 15 7 LlMII G W e Jai3 3 r TIT i 7 Ctt en en CI Ccff CEto C6 A...

Page 66: ...F by using the WR signal and Y6 signal see I O port description forming the STROMsignal and the chip select signal of each ROM is formed from the IO M signal by M5 TC40H139 The standard ROM is selecte...

Page 67: ...000H B FFFH C0OOH OFFFH E06OH ss s STANDARD ROM BANK OPTION fcAM 4f gfc Byte OpTloU RAM 2 CSK Byte feAM 1 C9K Byte OpTlOfvi ROM 32 B te RAHtf lCZK yte t frW RAM ff 4 y RAM fr 5 kwfrgfr 8c o Fwoh FFKFt...

Page 68: ...elect signals of circuits made by user 3I K YO L Device select signal for optional I O controller unit yFH Yl L Device select signal for optional answering telephone unit AFH Y2 L Bit 0 for ON OFF of...

Page 69: ...B1H or B9H Port A B2H or BAH Port B i B3H or BBH Port C i B4H or BCH Timer lower byte B5H or BDH Timer upper byte B6H B7H B8H and B9H Not used Table 23 6 Keyboard Key strobe signals are emitted from...

Page 70: ...n Jl R 1 a a A 1 OOOOOODa ll3KE 3 lL H l H l 1 1 H L M05 1 h a I Lpril Lf I Lfij Ln_ri Lpr in nl U mmn Lmm LmmmmJ IhhmJ i mi 1 I u CN R 1 Lfg LfJT LfpT Lr jgjff L 7 4c 4 i o t a L ui L L La 1 n L o lH...

Page 71: ...tegrator composed of R51 and C64 and after voltage division to the cassette AUX input level by R54 and R55 it is input at the AUX terminal see Fig 28 CMT connector 2 R54 R51 1 K 2 ciS K34 C63 i5 0 1A...

Page 72: ...data is sent to PAO PA7 of 81C55 and then as a result of data 1 write in to bit 1 of the output port 40H175 M14 indicated by I O address EOH EFH T8 is switched ON and an L level STROBE signal is sent...

Page 73: ...m the bar code is input ar d is then inverted by M34 after which RST 5 5 interruption occurs to indicate the start of data input Then when the bar code reader is moved on the bar code the H signal whi...

Page 74: ...zer drive caused by the output from PB5 of H L H L signals synchronized with the frequency for sounding the buzzer 2 Using 81C55 timer output With PB5 at H level in the circuit diagram Fig 33 the buzz...

Page 75: ...bus Pin No Signal Input or output Pin No Signal Input or i 1 VDD 40 VDD 2 GND 39 GND 3 ADO In output 38 AD1 In output 4 AD2 In output 37 AD3 In output 5 AD4 In output 36 AD5 In output 6 AD6 In output...

Page 76: ...ble 25 below shows the DC characteristic of each system bus signal i SO SI YO CLK Signals other than at left level output voltage VOH 2 4V min IOH 400uA 4 95 V min IOH lpA level output voltage VOL 0 4...

Page 77: ...for the interface with the LCD driver Fig 34 sH R1Ss3 V31 R154 33K 50K B 10K ADO AD7 For write in of control data or display data to the LCD driver signal line for read out from driver Y7 LCD driver e...

Page 78: ...ad write V2 Voltage to keep the LCD driver voltage standard LCD display can be changed by changing the V2 voltage by VR2 Figure 35 shows the operating timing of each signal Refere to the LCD PWB Techn...

Page 79: ...e All functions are enclosed in a 14 pin dual in line package a Features Marks time hours minutes seconds and calendar months date and day of the week Serial inputting and outputting of data Input out...

Page 80: ...Prohibition of data output DATA OUT terminal will become high impedance when the OUT ENABL is input Has no relation with other actions c Terminals Input terminals DATA IN Data input of 40 bit shift r...

Page 81: ...c2 o Ci o Cq o cs o 3 i 3 I 40 Bit Shift Register Multiplexer OSC CLK SD PS i i D W PS Month ps HD e PS I Hour I Mrn Z Time Counter 15 Stage Binary Divider TEST 1 JHz 32Hz 64HZ 56Hz Z s 8Hz V_ rOCOMM...

Page 82: ...the STB terminal becomes high level and will be held until a different command of the same group is written in f Data input output timing diagram Register Mode C2 C Cq set to 001 Shift Mode CS H CIK...

Page 83: ...D1990AC power supply the clock functions even when the Model 100 power switch is OFF The clock LSI C0 C2 terminals and DATA IN and CLK terminals are connected to the 81C55 PA0 PA4 terminals and the DA...

Page 84: ...ends the data of time and date information to the DATA IN terminal of UPD1990AC with timing clock PA3 Si Adz C19 0 047 APi 12v J 7 T CO CI C2 OATACtK Fig 41 1 Data Input o i r 20P 3 I C17 u 20P AT At...

Page 85: ...A CMC C18 it 20P 13 X 20P iH TTT Then the CPU sets to the data output mode with 100 pattern of C0 C2 and reads the data of tiir and date information from the DATA OUT terminal At the sa time the CPU s...

Page 86: ...UART LSI IM6402 and the CPU begins data transmission reception after the control word which determines the mode transmission reception is written into the control register selected by the Y5 signal _...

Page 87: ...4 TBR5 p4 TBR tI TBi T4 E WK wR When the TBRE signal becomes H data transmission is then possible so that if the transmission data is written into the transmitter buffer register TBR1 TBR8 the data is...

Page 88: ...rt M23 and if trere is no error when the serial data is received the reception data from the receive buffer register selected by Y4 can be read as 8 bit parallel data The IM6402 serial transmission re...

Page 89: ...only the circuit shown in Fig 43 is multiplexed to RS 232C and the MODEM RS 232C signal PB3 terminal of 81C55 determines whether the serial port is to Be used as RS 232C or as MODEM When the RS 232C...

Page 90: ...the IM6402 TRO signal and the 4 uw i RTS signal and from the DTR signal by the coupling capacitor V signals 0 039 uF 50 V the signals are leveled to 5 y tiie Schmitt trigger type inverter IC M35 and...

Page 91: ...o Send DSRR Data Set Ready DTRR Data Terminal R Application Data Output from RS 232C Data input to RS 232C The information below concerns the RS 232C driver and receiver Maximum distance transmission...

Page 92: ...lon On Chip Sin Warn Generator Modem Self Ttft Mod Singl Supply Voo 8 Vde MC14412FP MCU412FL Voo 4 7 10 8 0 Vde MC14413VP MC14412VL Selactabl Oata Rates 0 300 0 300 0400 bpi Post Detection Filter TTL...

Page 93: ...1 T Terminal Tranwnittar TuOata Ma4wlatov Ouoteaar Tetacttiona 1 Car 1 F Network UC14411 IK T rm na Ra Oata i Ownawjlata afwhiatf Fit tec and LlrwHef Format _ J Car Racaiwa Data PareHal Format L_ Fig...

Page 94: ...5 3 5 2 7S _ 3 5 _ V 1 0 or 9 0 Vdcl 10 7 0 7 0 530 _ 7 0 _ IVo 13 Of 13 5 Vdcl 15 11 0 11 0 8 35 _ 1 0 _ Pint 12 15 5 to IS 0 75 O S 2 0 0 85 Output Oriva Currant w OH mAdc IV H 2S Pin 7 5 0 S2 0 5 1...

Page 95: ...ther the U S or C C I T T operational frequencies for both transmitting and receiving data When the type input 1 the U S standard is selected and when the type input 0 the C C I T T standard is select...

Page 96: ...ata transmission this input should be low 0 The receive data output is digital data resulting from demodulation the Receive Carrier The receive carrier is the FSK input to the demodulation This input...

Page 97: ...al shunt capacitance must be 9PF at the crystal input To improve TTL interface compatibility all of the inputs to the MODEM have controllable P channel devices which act as pull up registors when TTLD...

Page 98: ...set to 300 bps and the U S Standard is selected Because the ECUO and SELF TEST terminals are not needed they are grounded level 0 The Q output EN signal of the port M36 selected by bit 1 of the Y2 por...

Page 99: ...ORIG ANS switch setting thus changing the value of R16 R28 and R25 The transmit carrier signal output from the TX CAR terminal is DC by C61 and the signal level is adjusted to 26 5 dB by the control V...

Page 100: ...t o p i...

Page 101: ...100 is used in the terminal mode avoids interference from the audio input signal from the telephone receiver by separating the signal TL from the telephone receiver RY2 separates the modem circuit an...

Page 102: ...f Dal Tun IS2076 T24 2603 R134 J I i NN U O R49 nr RT5M l M30 7 u l RX ID R M 9 f K C4 0 Fig 53 2 Direct Telephone and Terminal Mode...

Page 103: ...the forward direction This voltage causes the T21 and T22 base current to flow and the collector current is increased Although the collector current is increased in this way when it can longer increa...

Page 104: ...Power Detection and Automatic Power OFF Circuitry The low power detection circuit illuminates an LED warning lamp when the battery voltage decreases If it continues to decrease the system power will b...

Page 105: ...for 10 minutes or more awaiting a command for 10 minutes or more P C S is output from PB4 of 81C55 When the power switch is switched OFF T18 is switched OFF the M28 RESET terminal becomes L and oscill...

Page 106: ...i D23 i_ X A 1S2004FC 9 f O...

Page 107: ...h the result that the RESET signal changes from L to H This RESET waveform is inverted by T9 and is the RAM RST signal R141 provides hysteresis to the RESET signal Thermistor THz suppresses RESET sign...

Page 108: ...IM64 02 CMOS UART 423 TC40H244P CMOS LOGIC IC 424 TC40H032P CMOS LOGIC IC 125 81C55 CMOS PIO 42 6 TC4 0H002P CMOS LOGIC IC 127 4011 CMOS LOGIC IC 428 4 013 CMOS LOGIC IC 129 TL064CN O P AMP 130 TL0 64...

Page 109: ...SS2076 B QNHDK201AN QDSS2076 B 1S2076 SILICON DIODE 1S2004FC SILICON DIODE 2SA1115 TRANSISTOR 2SC2603 TRANSISTOR 1 2SC2603 TRANSISTOR 2SA1115 TRANSISTOR 2SC2603 E RANK TRANSISTOR 2SC2603 E RANK TRANSI...

Page 110: ...4W 5 CARBON FILM IK 1 4W 5 CARBON FILM 1 4K 1 4W 1 M OXIDE FILM 10K 1 4W 5 CARBON FILM 121K 1 4W 1 M OXIDE FILM 4 31K 1 4W 1 M OXIDE FILM 285K 1 4W 1 M OXIDE FILM 568K 1 4W 1 M OXIDE FILM 7 5K 1 4W 5...

Page 111: ...FILM 3 3K 1 4W 5 CARBON FILM 15M 1 4W 5 CARBON FILM 68K 1 4W 5 CARBON FILM 3 3K_1 4W 5 CARBON FILM 3 3K 1 4W 5 CARBON FILM 2 2K 1 4W 5 CARBON FILM Ik 1 4W 5 CARBON FILM 100K 1 4W 5 CARBON FILM 12K 1 4...

Page 112: ...4W 5 CARBON FILM 68K 1 4W 5 CARBON FILM 5 6K 1 4W 5 CARBON FILM 100 OHM 1 4W 5 CARBON FILM 18K 1 4W 5 CARBON FILM 27 OHM 1 4W 5 CARBON FILM 18K 1 4W 5 CARBON FILM 5 6K 1 4W 5 CARBON FILM 2 2K 1 4W 5...

Page 113: ...22K 1 4W 5 CARBON FILM 33K 1 4W 5 CARBON FILM 10K 1 4W 5 CARBON FILM 22K 1 4W 5 CARBON FILM IK 1 4W 5 CARBON FILM 150K 1 4W 5 CARBON FILM NOT USED 3 3K 1 4W 5 CARBON FILM 68K 1 4W 5 CARBON FILM 62K 1...

Page 114: ...ITOR 20pF 50V CERMIC CAPACITOR 20pF 50V CERMIC CAPACITOR 0 047UF 12V CERMIC CAPACITOR 500pF 50V CERMIC CAPACITOR 500pF 50V CERMIC CAPACITOR 500pF 50V CERMIC CAPACITOR 500pF 50V CERMIC CAPACITOR 500pF...

Page 115: ...ERMIC CAPACITOR O luF 50V 10 MYLAR CAPACITOR 0 0 47uF 50V 10 MYLAR CAPACITOR 0 0 47uF 12V CERMIC CAPACITOR 0 0 47UF 12V CERMIC CAPACITOR O C47uF 12V CERMIC CAPACITOR 1000 pF 50V CERMIC CAPACITOR IGOOp...

Page 116: ...0 47uF 50V ELYT CAPACITOR CEVGR47ADN C93 100 pF 50V 10 MICA CAPACITOR CMDA10 1KXB C94 0 0047uF 25V CERMIC CAPACITOR CBD1E472MM C95 O luF 250V 20 POLYESTER CAPACITOR CQHD10 4MEN C96 O luF 250V 20 POLYE...

Page 117: ...Ni cd BATTERY HECO 34 2 01 010 JACK A 8878A 28S 1H IC SOCKET MANUFACTURER S PART NUMBER YJF30SO06Z ZBN0 3610 2Y YJB0 3S0 01Z YSC28S002Z RADIO SHACK PART NUMBER IC SOCKET IC SOCKET IC SOCKET BATTERY T...

Page 118: ...y SECTION IV LCD P W BOARD...

Page 119: ...it possesses the properties of a crystal Items which use this liquid crystal are liquid crystal display elements The LCD used in Model 100 is a TN Twisted Nematic type of liquid crystal Its basic cons...

Page 120: ...2 As shown in Fig 2 a if voltage is not applied the liquid crystal molecules between the upper and lower plates twist 90 to distribute light This results in a 90 optical movement of the light 3 In ot...

Page 121: ...operates on a 1 32 duty time division drive the upper 32 and lower 32 back scanning is performed by the same signal n 240 IT J2 240 Com on Segment Segment Common 16 Fig 3 LCD electrodes The angle of t...

Page 122: ...age 7 6 30 Fig 4 LCD VoHrA e low Caution The polarization plate attached to the surface of the LCD panel is scratched very easily and so must be handled with great care To clean contacts or the displa...

Page 123: ...signal outputs Mil and M12 are cascade connected and a 1 32 duty back scan signal is made By using a C and R only at the Mil side a timing signal is generated and Ml 2 is controlled by that signal Mi...

Page 124: ...econd For Model 100 FRM 70 Hz The 1 and 2 signals are the locks for HD44102 RAM operation The CL signal is the shift lock for the shift register ICs Ml M10 HD44102 are segment driver ICs that cause th...

Page 125: ...h upper and lower the M5 and M10 segment output Y41 Y50 becomes NOCONNECTION The power supplied to these ICs in addition to V DD 5 V and V E 5 V also includes VI V6 V DD and V EE are the power supplie...

Page 126: ...22 C3 C4 C6 C7 and C8 augment the peak current during LCD illumination Rll R12 and R13 are resistors for IC latch up prevention This board also includes a low power detection LED and buzzer connector...

Page 127: ...ot in question is affected by crosstalk display information from other dots on the same display line In order to suppress such crosstalk it is necessary that the voltage applied as effective voltage t...

Page 128: ...e 1 Liquid crystal voltages and voltages applied to each electrode by the voltage averaging method As can be understood by studying Table 1 the voltages applied to the liquid crystal 32 1 time for non...

Page 129: ...ontrast the maximum ratio between the illumination voltage and the non illumination voltage When that ratio is greatest in relation to the effective ON and OFF voltages a 6 66 Thus for VI V2 V3 V4 V5...

Page 130: ...1 4W 5 CARBON FILM O luF 25V CHIP CAPACITOR O luF 25V CHIP CAPACITOR 18pF 25V CHIP CAPACITOR O luF 25V CHIP CAPACITOR O luF 25V _ CHIP CAPACITOR LR20 2 C L C D L C D CONNECTOR L C D HOLDER SLP 135B L...

Page 131: ...SECTION VII DIAGRAMS...

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Page 133: ...PLX110CH1X 9...

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Page 136: ...ZSS 5...

Page 137: ...it rr t r 3 J 9 A i r X r 1 f f V i 7S h i s r 3 u IT r C 7 r 3 7 y E V _l l T...

Page 138: ...rifEr T s ii fj5 S14 i E il 3 1 I fclr 75S r oaSsS S i_y IS f f s J 02 j l f Q j n M 2 IBuir V lll ll l l r iOn I f I j zrr I FI G U f f s f _ Ste tit f 3x3tJS J j ft fe t fTF Cn r 4 1 r fHK H rarffit...

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Page 141: ...AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Model 100 Preliminary Diagnostics AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA...

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Page 143: ...word BASIC and press ENTER 4 In BASIC type POWER CONT ENTER 5 Type CLEAR 200 60000 ENTER 6 Type CLOADM MEMLO ENTER 7 Once the program loads without error type CALL 61440 ENTER 8 At the Model 100 Memo...

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Page 145: ...THAT YOU WISH TO RETAIN SAVE THEM FIRST Loading and Executing 1 Prepare cassette player and cassette tape 2 Power up the Model 100 3 At the Model 100 power up menu type BASIC ENTER OR position the cu...

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Page 147: ...ith zeros and then read the RAM to make sure that the zeros were written The second test is the FF Fill and operates in the same manner except that it uses FF hex to fill memory instead of zero The la...

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Page 149: ...op left corner of the menu Use the arrow keys to insure the the cursor is positioned over the word BASIC and hit the ENTER key If the main menu is NOT displayed try pressing F8 This should return you...

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Page 151: ...3 This test puts patterns into the LCD display memory This just verifies that every dot can be turned on If in doubt try directly addressing a point on the screen with your own BASIC program CLOCK TES...

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Page 153: ...to the printer Printer must be BAR CODE READER 8 This test displays number patterns that the bar code reader is being swept over properly Make sure that the wand is moved smoothly over the pattern an...

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Radio Shack 26-3801, Service Manual

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