Rabbit Rabbit 4000, User Manual

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Chapter 25 Breakpoints 263
25. B
REAKPOINTS
25.1 Overview
The Rabbit 4000 contains seven hardware breakpoints to support debugging. Each hard-
ware breakpoint consists of a 24-bit address match register and a 24-bit mask register. A
breakpoint can be generated on an address match for address execution, data read, data
write, or any combination thereof. The mask register serves to mask off selected address
bits from the address compare. A “one” in a particular bit position in the mask register
inhibits the corresponding bit in the address match register from contributing to the
address match condition.
When a match occurs, a Level 3 breakpoint interrupt is generated. Note that this means
that breakpoints behave differently when the processor is running at Interrupt Priority 3 —
the interrupt is generated but will not be handled until the processor drops to a lower priority.
In most cases, a code execution interrupt will be handled at the end of the instruction in
which the match occurred. However, because of the time required to perform a 24-bit
address match in the processor, a code execution breakpoint that is set on a single-byte,
2-clock instruction will not yet be enabled at the end of that instruction, and the interrupt
will instead occur at the end of the next instruction.
Note that a breakpoint may be forced to be pending by setting the corresponding bit in
BDCR. This feature allows a breakpoint request to be used as a virtual single-step request
by always setting the appropriate bit in the interrupt handler. There is a particular sequence
of instructions required to exit properly when the interrupt is left pending.
DMA transfers are treated as normal data reads and writes, although the DMA transfer
will complete before the interrupt is taken.
Breakpoints can be enabled for the User Mode, the System Mode, or both.
Another breakpoint feature is the ability to disable the RST 28h instruction. The RST 28h
vector was often used as a breakpoint feature by adding that instruction to code; by
enabling a bit in BDCR, the RST 28h instruction will execute as a NOP instead, providing
an easy way to disable that type of breakpoint.
Note that hardware breakpoints do not differentiate between memory and I/O accesses.
Hardware breakpoints are triggered by both memory and by internal I/O reads and writes.
This behavior could potentially make it hard to detect a low-memory situation when using
breakpoints if internal I/O reads/writes are occurring, but it allows inadvertent I/O
accesses to be identified.