Rabbit 3000, User Manual

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194 Rabbit 3000 Microprocessor
15.1 Power Supply Connections and Board Layout
The Rabbit die and package are schematically shown in Figure 15-1 below. The die is
divided into two power supply regions, the core and I/O ring. (A third power-supply
region, the battery-backable region exists but is not important for EMI.) The core is pro-
vided power by means of 8 pins, 4 of which are grounds and 4 of which provide nominal
3.3 V power. The I/O ring has 8 ground pins and 7 power pins. The package pins are con-
nected to bonding pads on the silicon die by thin bond wires. The connections consisting
of the bond wires and the package lead frame exhibit an inductance of about 5 nH.
Figure 15-1. Division of Rabbit 3000 Die and Package
The core contains fast logic and switches large currents synchronous with the clock edges.
The core generates considerable high-frequency noise, which can pass outside the package
via the core power and ground pins. The I/O ring contains the buffers that drive the pack-
age pins. The buffers typically operate at lower frequencies with slower rise times than the
core logic. Noise on the power supply rails in the I/O ring will be passed through the buff-
ers and appear on the output pins.
In a low-EMI design, there should be a power and ground plane in the PC board. The
power and ground plane distribute power and ground to all the components on the PC
board, including drivers that drive wires exiting from the PC board. It is important to min-
imize the high-frequency noise on the power and ground distribution to prevent EMI. The
basic method of doing this is to filter the core power pins to block noise from reaching the
PC board. The I/O ring is then connected to the PC power distribution with a low-
inductance connection. Noise on the I/O ring power supply will be communicated to every
output pin on the package, so it is important to minimize the level of I/O ring supply noise.
It is suggested that the power pins for the core and the I/O supply be connected to the sup-
ply planes and decoupling capacitors in a different fashion as shown in Figure 15-2 below.
By placing the decoupling capacitor for the core before the connection is made to the
bond wire
pin
package
core
I/O Ring
silicon die