QM1004-2-18 Combined RF Upconverter/Downconverter
User Manual
3. System Block Diagram
System block diagrams for the QM1004-2-18 Combined RF Upconverter/Downconverter are shown in
Figures 1.2 and 1.3. Internal attenuators in the upconverter and downconverter blocks are controlled
digitally via a microcontroller, which interfaces to a PC through USB or TCP/IP. The microcontroller out-
puts basic status messages on a 32-character Liquid Crystal Display (LCD) mounted on the faceplate of
the unit. An internal 100 MHz reference clock is phase-locked to all of the internal LOs, with a BNC-F
connector providing the option for LOs to lock to a user-provided 10-250 MHz external reference. Two
additional BNC-F connectors output an internally-generated 10 MHz and 100 MHz reference for use by
external test equipment. Switching between the internal and external LO reference clocks is controlled
either by the microcontroller or a reference selector switch. The 12-20 GHz LO1 output is provided for
external phase locking.
Figure 1.2:
QM1004–2–18 Upconverter Block Diagram
Figure 1.3:
QM1004–2–18 Downconverter Block Diagram
Quonset Microwave
Revision 6.1.0
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