Smart LTE Module Series
SC66 Hardware Design
SC66_Hardware_Design 81 / 139
1. CSI2_LN2_P/N, CSI2_LN3_P/N can be multiplexed into MIPI signal lines of the fourth camera.
2. LN2 can be configured as DATA, LN3 as CLK and GPIO_34 as MCLK.
3. I2C interfaces are connected with CAM_I2C_SDA1 and CAM_I2C_SCL1.
4. Reset and PWDN signals are configured by using general-purpose GPIOs.
3.20.1. Design Considerations
Special attention should be paid to the pin definition of LCM/camera connectors. Assure the SC66
and the connectors are correctly connected.
MIPI are high speed signal lines, supporting maximum data rate up to 2.1Gbps. The differential
impedance should be controlled to 85Ω. Additionally, it is recommended to route the trace on the
inner layer of PCB, and do not cross it with other traces. For the same group of DSI or CSI signals, all
the MIPI traces should keep the same length.
Be assure the reference ground plane for CSI/DSI is complete and integral, without any cut or void.
Route the camera CLK signal in the inner layer of the PCB between ground fills
Route CSI and DSI traces according to the following rules:
a) The intra-pair spacing should be one-time the trace width
b) The inter-pair spacing should be 1.5 times the trace width
c) The spacing to other signal lines should be 2.5 times the trace width
Route MIPI traces according to the following rules:
a) The CSI trace length should not exceed 170mm and the DSI trace length should not exceed
110mm;
b)
Control the differential impedance to 85Ω±10%;
c) Control intra-lane length difference within 0.7mm;
d) Control inter-lane length difference within 1.4mm.
Table 28: Trace Length of MIPI Differential Pairs Inside the Module
Pin No.
Signal
Length (mm)
Length Difference (P-N)
116
DSI0_CLK_N
27.35
-0.05
115
DSI0_CLK_P
27.30
118
DSI0_LN0_N
27.00
0.00
117
DSI0_LN0_P
27.00
120
DSI0_LN1_N
26.65
-0.05
119
DSI0_LN1_P
26.60
NOTES
