Smart Module Series
SC262R_Series_Hardware_Design 61 / 115
CSI1_LN3_N
70
AI
MIPI CSI1 lane 3 data (-)
CSI1_LN3_P
71
AI
MIPI CSI1 lane 3 data (+)
CSI1_LN2_N
72
AI
MIPI CSI1 lane 2 data (-)
CSI1_LN2_P
73
AI
MIPI CSI1 lane 2 data (+)
CSI0_CLK_N
157
AI
MIPI CSI0 clock (-)
CSI0_CLK_P
196
AI
MIPI CSI0 clock (+)
CSI0_LN0_N
158
AI
MIPI CSI0 lane 0 data (-)
CSI0_LN0_P
197
AI
MIPI CSI0 lane 0 data (+)
CSI0_LN1_N
159
AI
MIPI CSI0 lane 1 data (-)
CSI0_LN1_P
198
AI
MIPI CSI0 lane 1 data (+)
CSI0_LN2_N
160
AI
MIPI CSI0 lane 2 data (-)
CSI0_LN2_P
199
AI
MIPI CSI0 lane 2 data (+)
CSI0_LN3_N
161
AI
MIPI CSI0 lane 3 data (-)
CSI0_LN3_P
200
AI
MIPI CSI0 lane 3 data (+)
CAM0_MCLK
74
DO
Master clock of camera0
1.8 V power domain.
CAM1_MCLK
75
DO
Master clock of camera1
CAM0_RST
79
DO
Reset of camera0
CAM0_PWDN
80
DO
Power down of camera0
CAM1_RST
81
DO
Reset of camera1
CAM1_PWDN
82
DO
Power down of camera1
CAM_I2C_SCL
83
OD
I2C clock of front and rear
cameras
Externally pull them
up to 1.8 V.
CAM_I2C_SDA
84
OD
I2C data of front and rear
cameras
CAM2_MCLK
165
DO
Master clock of camera2
1.8 V power domain.
CAM2_RST
164
DO
Reset of camera2
CAM2_PWDN
163
DO
Power down of camera2
