Smart Module Series
SC20_Series_Hardware_Design 35 / 133
below 3.1 V.
Figure 3: Voltage Drop Sample
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip capacitor (MLCC) should also be reserved due to its ultra-low ESR. It
is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array,
and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from the external
application must be a single voltage source and can be expanded to two sub paths with star structure.
The width of VBAT_BB trace should be no less than 1.5 mm, and the width of VBAT_RF trace should be
no less than 2 mm. In principle, the longer the VBAT trace is, the wider it should be.
In addition, in order to get a stable power source, it is suggested to use a TVS diode and place it as close
to the VBAT_BB/VBAT_RF pins as possible to increase voltage surge withstand capability. The following
figure shows the star structure of the power supply.
Module
VBAT_RF
VBAT_BB
VBAT
C1
100
μF
C6
100 nF
C7
33 pF
C8
10 pF
+
+
C2
100 nF
C5
100
μ
F
C3
33 pF
C4
10 pF
D1
Figure 4: Star Structure of the Power Supply
