5G Module Series
RM502Q-GL Hardware Design
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Table 11: Pin Definition of PCM Interface*
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer
to
document [2]
for details about
AT+QDAI
command.
“*” means under development.
3.10. Control and Indication Interfaces
The following table shows the pin definition of control and indication pins.
Table 12: Pin Definition of Control and Indication Interfaces
Pin No. Pin Name
I/O
Description
Comment
20
PCM_CLK
IO
PCM data bit clock
1.8 V power domain
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
22
PCM_DIN
DI
PCM data input
1.8 V power domain
24
PCM_DOUT
DO
PCM data output
1.8 V power domain
28
PCM_SYNC
IO
PCM data frame sync
1.8 V power domain
Pin No.
Pin Name
I/O
Description
Comment
8
W_DISABLE1#*
DI
Airplane mode control. Active LOW.
1.8/3.3 V
10
WWAN_LED#*
OD
It is an open drain and active low signal.
Indicate RF status of the module.
23
WAKE_ON_WAN#*
OD
Wake up the host.
It is an open drain and active low signal.
25
DPR*
DI
Dynamic power reduction. High level by
default.
1.8 V
26
W_DISABLE2#*
DI
GNSS disable control. Active LOW.
1.8/3.3 V
38
SDX2AP_STATUS
DO
Status indication to AP
1.8 V power
domain
NOTE
