LPWA Module Series
BG952A-GL_QuecOpen_Hardware_Design
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Table 16: Pin Definition of CLI UART Interface
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if your application
is equipped with a 3.3 V UART interface. It is recommended to use a level conversion chip without
internal pull-up. The voltage-level translator TXB0108PWR provided by
Texas Instruments
is
recommended. The following figure shows a reference design of the main UART interface:
Figure 17: Main UART Reference Design (Translator Chip)
Visit http://www.ti.com for more information on the translator chip.
Another example with transistor circuit is shown as below. For the design of circuits in dotted lines, refer to
that of circuits in solid lines, but pay attention to the direction of connection.
MAIN_RI
*
39
DO
Main UART ring indication
Pin Name
Pin No.
I/O
Description
Comment
CLI_TXD2
95
DO
CLI UART2 transmission
1.8 V power domain.
If unused, keep them
open.
CLI_RXD2
94
DI
CLI UART2 reception
CLI_TXD1
27
DO
CLI UART1 transmission
1.8 V power domain.
If unused, keep them
open.
CLI_RXD1
28
DI
CLI UART1 reception
